Abstract: A flash memory having high reliability and a method for controlling the flash memory is provided for seeking stability of memory cell threshold voltage distribution. A NAND string of the flash memory has: a source-line-side select transistor; a source-line-side dummy cell; a plurality of memory cells; a bit-line-side dummy cell; and a bit-line-side select transistor. A method for controlling the flash memory includes the following step: after erasing a selected block, programming the dummy cell of the selected block into a programmed state by applying a programming voltage to a dummy word line which is connected to the dummy cell.

Abstract: A flash memory of the invention has a plurality of planes, a controller, a switch unit, and a driving control circuit. The controller is configured to select at least one of the planes. The switch unit is configured to electrically connect bit lines of the unselected plane to a reference voltage. The driving control circuit is configured to commonly provide a gate select signal to select transistors of the selected planes and the unselected planes after the bit lines of the unselected plane is electrically connected to the reference voltage. Accordingly, a flash memory that can reliably seek stability of threshold distribution of memory is provided.

Abstract: A program method capable of reducing a peak current of a program operation is provided. The program method of a flash memory includes following steps: charging selective bit lines and non-selective bit lines by using a virtual voltage with weak driving ability during the time from t0 to t1 and a virtual voltage with strong driving ability during the time from t1 to t2, switching at least the non-selective bit lines to use the virtual voltage with weak driving ability for charging during at least the time from t2 to t3 when starting to discharge the selective bit lines connected to selective storage cells to a GND voltage level at time t2, and then applying program voltages to selective word lines.

Abstract: A voltage generating circuit, a semiconductor storage device, and a bit line charging method thereof are provided. The voltage generating circuit includes: an INTVDD generating circuit for generating an internal power supply voltage INTVDD from an external power supply voltage EXVDD; a VDD_V1 generating circuit for generating an internal power supply voltage VDD_V1 from the external power supply voltage EXVDD; and a V1_driving circuit generating a charging voltage for charging the bit line at an output node by using the internal power supply voltage VDD_V1. The V1_driving circuit may generate voltages V1 having different driving capability. The V1_driving circuit charges the bit line with the voltage V1 having a weak driving capability during a first charging period of the bit line and charges the bit line with the voltage V1 having a strong driving capability during a second charging period.

Abstract: A level shifter includes a pair of cross-coupled PMOS transistors, intrinsic-type NMOS transistors, an input node, a control circuit and an output node. A high voltage is supplied to the PMOS transistors. The intrinsic-type NMOS transistors and the PMOS transistors are respectively coupled in serial. The input node is configured to receive input signals. The control circuit is triggered by the voltage Vdd and is configured to generate enable signals and control signals according to the input signal. The output node is configured to output the high Voltage HV or the GND voltage as the output signal. After the node aa is charged, the transistor HVNI_1 is turned off according to the control signal SW to avoid leakage current being generated. After the node MOUT is charged, the transistor HVNI_2 is turned off according to the control signal SWb to avoid leakage current being generated.

Abstract: The present invention utilizes a new method to provide a semiconductor device having a function of generating inherent data. The NAND-type flash memory of the present invention has a memory cell array, a page buffer/sense circuit, and a differential sense amplifier that detects the potential difference of a bit line pair of a dummy array when the dummy array of the memory cell array is read out, wherein the NAND-type flash memory outputs the inherent data of the semiconductor device according to the detection result of the differential sense amplifier.

Abstract: A semiconductor memory device for suppressing the peak current during the read operation is provided. A flash memory of the disclosure includes a memory cell array; a plurality of charge pump circuits; and a controller controlling a timing of activating the charge pump circuits when a selected page of the memory cell array is read so that the charge pump circuits are not activated at the same timing.

Abstract: A level shifter includes a pair of cross-coupled PMOS transistors, intrinsic-type NMOS transistors, an input node, a control circuit and an output node. A high voltage is supplied to the PMOS transistors. The intrinsic-type NMOS transistors and the PMOS transistors are respectively coupled in serial. The input node is configured to receive input signals. The control circuit is triggered by the voltage Vdd and is configured to generate enable signals and control signals according to the input signal. The output node is configured to output the high Voltage HV or the GND voltage as the output signal. After the node aa is charged, the transistor HVNI_1 is turned off according to the control signal SW to avoid leakage current being generated. After the node MOUT is charged, the transistor HVNI_2 is turned off according to the control signal SWb to avoid leakage current being generated.

Abstract: A cache memory includes a CAM with an associativity of n (where n is a natural number) and an SRAM, and storing or reading out corresponding data when a tag address is specified by a CPU connected to the cache memory, the tag address constituted by a first sub-tag address and a second sub-tag address. The cache memory classifies the data, according to the time at which a read request has been made, into at least a first generation which corresponds to a read request made at a recent time and a second generation which corresponds to a read request made at a time which is different from the recent time. The first sub-tag address is managed by the CAM. The second sub-tag address is managed by the SRAM. The cache memory allows a plurality of second sub-tag addresses to be associated with a same first sub-tag address.

Abstract: A cache memory includes a CAM with an associativity of n (where n is a natural number) and an SRAM, and storing or reading out corresponding data when a tag address is specified by a CPU connected to the cache memory, the tag address constituted by a first sub-tag address and a second sub-tag address. The cache memory classifies the data, according to the time at which a read request has been made, into at least a first generation which corresponds to a read request made at a recent time and a second generation which corresponds to a read request made at a time which is different from the recent time. The first sub-tag address is managed by the CAM. The second sub-tag address is managed by the SRAM. The cache memory allows a plurality of second sub-tag addresses to be associated with a same first sub-tag address.