Patents by Inventor Shoa-Siong Raymond Lim
Shoa-Siong Raymond Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10154588Abstract: A manufacturing method of a semiconductor package includes the following steps. Firstly, a conductive carrier is provided. Then, a first conductive layer is formed on a lower surface of the conductive carrier. Then, a second conductive layer is formed on a lower surface of the first conductive layer, wherein the second conductive layer and the first conductive layer together constitute a conductive structure. Then, an electrical component is disposed on the lower surface of the first conductive layer. Then, a first package body encapsulating the first conductive layer, the second conductive layer and the electrical component but not covering an edge of the lower surface of the conductive carrier is formed. Then, a portion of the first package body is removed. Then, partial material of the conductive carrier is removed, such that a reserved part of the conductive carrier forms a ring-shaped conductive structure.Type: GrantFiled: June 29, 2017Date of Patent: December 11, 2018Assignee: ADVANPACK SOLUTIONS PTE LTD.Inventors: Hwee-Seng Jimmy Chew, Shoa-Siong Raymond Lim
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Patent number: 9892916Abstract: A manufacturing method of a package substrate is provided. A conductive substrate is provided. A first photoresist layer is patterned to form first openings. A first conductive layer is formed in the first openings. A second photoresist layer is patterned to form second openings. A second conductive layer contacting the first conductive layer is formed in the second openings. The first and second photoresist layers are removed. A dielectric layer covers the first, second conductive layers and a portion of the conductive substrate. A portion of the dielectric layer is removed. A third photoresist layer is patterned to form a third opening. A portion of the conductive substrate is removed to form a fourth opening. The third photoresist layer is removed. A fourth photoresist layer is patterned to form a fifth opening. A bonding pad is formed in the fifth opening. The fourth photoresist layer is removed.Type: GrantFiled: June 15, 2016Date of Patent: February 13, 2018Assignee: ADVANPACK SOLUTIONS PTE LTD.Inventors: Shoa-Siong Raymond Lim, Hwee-Seng Jimmy Chew
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Publication number: 20170330842Abstract: A semiconductor structure and a method of fabricating the same. The semiconductor structure comprises: a layer element, one or more supporting elements disposed on a first surface of the layer element, and one or more anchoring elements disposed within the layer element and connected to the one or more supporting elements to couple the one or more supporting elements to the layer element to strengthen the layer element.Type: ApplicationFiled: July 20, 2017Publication date: November 16, 2017Inventors: Shoa Siong Raymond Lim, Hwee Seng Jimmy Chew
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Publication number: 20170303399Abstract: A manufacturing method of a semiconductor package includes the following steps. Firstly, a conductive carrier is provided. Then, a first conductive layer is formed on a lower surface of the conductive carrier. Then, a second conductive layer is formed on a lower surface of the first conductive layer, wherein the second conductive layer and the first conductive layer together constitute a conductive structure. Then, an electrical component is disposed on the lower surface of the first conductive layer. Then, a first package body encapsulating the first conductive layer, the second conductive layer and the electrical component but not covering an edge of the lower surface of the conductive carrier is formed. Then, a portion of the first package body is removed. Then, partial material of the conductive carrier is removed, such that a reserved part of the conductive carrier forms a ring-shaped conductive structure.Type: ApplicationFiled: June 29, 2017Publication date: October 19, 2017Applicant: ADVANPACK SOLUTIONS PTE LTD.Inventors: Hwee-Seng Jimmy CHEW, Shoa-Siong Raymond LIM
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Patent number: 9754899Abstract: A semiconductor structure and a method of fabricating the same. The semiconductor structure comprises: a layer element, one or more supporting elements disposed on a first surface of the layer element, and one or more anchoring elements disposed within the layer element and connected to the one or more supporting elements to couple the one or more supporting elements to the layer element to strengthen the layer element.Type: GrantFiled: February 21, 2014Date of Patent: September 5, 2017Assignee: Advanpack Solutions PTE LTDInventors: Shoa Siong Raymond Lim, Hwee Seng Jimmy Chew
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Substrate structure, semiconductor package device, and manufacturing method of semiconductor package
Patent number: 9723717Abstract: A substrate structure, a semiconductor package and a manufacturing method of semiconductor package are provided. The substrate structure comprises a conductive structure, an electrical component, a package body and a ring-shaped conductive structure. The conductive structure comprises a first conductive layer and a second conductive layer. The first conductive layer has a lower surface. The second conductive layer and the electrical component are formed on the lower surface of the first conductive layer. The package body encapsulates the conductive structure and the electrical component and has an upper surface. The ring-shaped conductive structure surrounds the conductive structure and the electrical component and is disposed at the edge of the upper surface of the package body to expose the conductive structure.Type: GrantFiled: December 19, 2012Date of Patent: August 1, 2017Assignee: ADVANPACK SOLUTIONS PTE LTD.Inventors: Hwee-Seng Jimmy Chew, Shoa-Siong Raymond Lim -
Patent number: 9653323Abstract: A manufacturing method of a substrate structure is provided. The method includes the following steps. Firstly, a conductive carrier is provided. Then, a first metal layer is formed on the conductive carrier. Then, a second metal layer is formed on the first metal layer. Then, a third metal layer is formed on the second metal layer, wherein each of the second metal layer and the third metal layer has a first surface and a second surface opposite to the first surface, the first surface of the third metal layer is connected to the second surface of the second metal layer, the surface area of the first surface of the third metal layer is larger than the surface area of the second surface of the second metal layer, and the first metal layer, the second metal layer and the third metal layer form a conductive structure.Type: GrantFiled: March 4, 2016Date of Patent: May 16, 2017Assignee: ADVANPACK SOLUTIONS PTE LTD.Inventors: Hwee-Seng Jimmy Chew, Shoa-Siong Raymond Lim
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Patent number: 9583449Abstract: A semiconductor package includes a dielectric layer, a plurality of traces, a plurality of electrical pads, a plurality of studs and at least a semiconductor device. The dielectric layer has a first dielectric surface and a second dielectric surface opposite the first dielectric surface. The traces are disposed in the dielectric layer and are exposed on the second dielectric surface. The electrical pads are disposed on the first dielectric surface. The studs are disposed in the dielectric layer and are exposed on the first dielectric surface. The studs are electrically connected to the traces and the electrical pads. The semiconductor device is disposed on the second dielectric surface and electrically connected to the traces.Type: GrantFiled: December 7, 2015Date of Patent: February 28, 2017Assignee: ADVANPACK SOLUTIONS PTE LTD.Inventors: Hwee-Seng Jimmy Chew, Kian-Hock Lim, Oviso Dominador Fortaleza, Jr., Shoa-Siong Raymond Lim
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Publication number: 20160293416Abstract: A manufacturing method of a package substrate is provided. A conductive substrate is provided. A first photoresist layer is patterned to form first openings. A first conductive layer is formed in the first openings. A second photoresist layer is patterned to form second openings. A second conductive layer contacting the first conductive layer is formed in the second openings. The first and second photoresist layers are removed. A dielectric layer covers the first, second conductive layers and a portion of the conductive substrate. A portion of the dielectric layer is removed. A third photoresist layer is patterned to form a third opening. A portion of the conductive substrate is removed to form a fourth opening. The third photoresist layer is removed. A fourth photoresist layer is patterned to form a fifth opening. A bonding pad is formed in the fifth opening. The fourth photoresist layer is removed.Type: ApplicationFiled: June 15, 2016Publication date: October 6, 2016Applicant: ADVANPACK SOLUTIONS PTE LTD.Inventors: Shoa-Siong Raymond LIM, Hwee-Seng Jimmy CHEW
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Publication number: 20160189981Abstract: A manufacturing method of a substrate structure is provided. The method includes the following steps. Firstly, a conductive carrier is provided. Then, a first metal layer is formed on the conductive carrier. Then, a second metal layer is formed on the first metal layer. Then, a third metal layer is formed on the second metal layer, wherein each of the second metal layer and the third metal layer has a first surface and a second surface opposite to the first surface, the first surface of the third metal layer is connected to the second surface of the second metal layer, the surface area of the first surface of the third metal layer is larger than the surface area of the second surface of the second metal layer, and the first metal layer, the second metal layer and the third metal layer form a conductive structure.Type: ApplicationFiled: March 4, 2016Publication date: June 30, 2016Applicant: ADVANPACK SOLUTIONS PTE LTD.Inventors: Hwee-Seng Jimmy CHEW, Shoa-Siong Raymond LIM
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Patent number: 9379044Abstract: A package substrate including a dielectric layer, a first conductive layer, a second conductive layer and a bonding pad is provided. The dielectric layer has a top surface and a bottom surface. The first conductive layer is embedded into the dielectric layer, and a first surface of the first conductive layer is exposed from the top surface and has the same plane with the top surface. The second conductive layer is embedded into the dielectric layer and contacts the first conductive layer, and a second surface of the second conductive layer is exposed from the bottom surface and has the same plane with the bottom surface. The bonding pad is partially or completely embedded into the first conductive layer and the dielectric layer, so that the periphery of the bonding pad is confined within a cavity by the sidewalls of both the first conductive layer and the dielectric layer.Type: GrantFiled: October 20, 2012Date of Patent: June 28, 2016Assignee: ADVANPACK SOLUTIONS PTE LTD.Inventors: Shoa-Siong Raymond Lim, Hwee-Seng Jimmy Chew
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Publication number: 20160118349Abstract: A semiconductor package includes a dielectric layer, a plurality of traces, a plurality of electrical pads, a plurality of studs and at least a semiconductor device. The dielectric layer has a first dielectric surface and a second dielectric surface opposite the first dielectric surface. The traces are disposed in the dielectric layer and are exposed on the second dielectric surface. The electrical pads are disposed on the first dielectric surface. The studs are disposed in the dielectric layer and are exposed on the first dielectric surface. The studs are electrically connected to the traces and the electrical pads. The semiconductor device is disposed on the second dielectric surface and electrically connected to the traces.Type: ApplicationFiled: December 7, 2015Publication date: April 28, 2016Applicant: ADVANPACK SOLUTIONS PTE LTD.Inventors: Hwee-Seng Jimmy CHEW, Kian-Hock LIM, Oviso Dominador Jr FORTALEZA, Shoa-Siong Raymond LIM
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Patent number: 9301391Abstract: A substrate structure includes first, second and third metal layers embedded in a dielectric layer between its opposite upper first and lower second surfaces. The entire upper surface of the first metal layer is exposed on the first surface of the dielectric layer, the entire lower surface of the third metal layer is exposed on the second surface of the dielectric layer, and the second metal layer is disposed between the first metal layer and the third metal layer, wherein the area of the third metal layer is larger than the area of the second metal layer.Type: GrantFiled: November 29, 2012Date of Patent: March 29, 2016Assignee: ADVANPACK SOLUTIONS PTE LTD.Inventors: Hwee-Seng Jimmy Chew, Shoa-Siong Raymond Lim
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Publication number: 20160013139Abstract: A semiconductor structure and a method of fabricating the same. The semiconductor structure comprises: a layer element, one or more supporting elements disposed on a first surface of the layer element, and one or more anchoring elements disposed within the layer element and connected to the one or more supporting elements to couple the one or more supporting elements to the layer element to strengthen the layer element.Type: ApplicationFiled: February 21, 2014Publication date: January 14, 2016Applicant: ADVANPACK SOLUTIONS PTE LTDInventors: Shoa Siong Raymond Lim, Hwee Seng Jimmy Chew
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Patent number: 9219027Abstract: The semiconductor device carrier comprises a conductive carrier, a dielectric layer, a conductive trace layer, a conductive stud layer and the plating conductive layer. The conductive carrier comprises at least one cavity. The dielectric layer has a first dielectric surface and a second dielectric surface opposite the first dielectric surface. The conductive trace layer disposes in the dielectric layer and is exposed on the second dielectric surface. The conductive stud layer disposes in the dielectric layer and is exposed on the first dielectric surface, wherein the conductive stud layer is electrically connected to the conductive trace layer. The plating conductive layer is disposed on the first dielectric surface and the exposed conductive stud layer. The cavity exposes the conductive trace layer and the dielectric layer.Type: GrantFiled: February 20, 2014Date of Patent: December 22, 2015Assignee: ADVANPACK SOLUTIONS PTE LTD.Inventors: Hwee-Seng Jimmy Chew, Kian-Hock Lim, Oviso Dominador Jr Fortaleza, Shoa-Siong Raymond Lim
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Publication number: 20150348895Abstract: A method of forming a substrate (10) for semiconductor packaging and a substrate (10) for semiconductor packaging are provided. The method includes providing a carrier (12) and forming a plurality of external pads (14) on the carrier (12), the external pads (14) formed on the carrier (12) defining a first conductive layer. A molding operation is performed to form a first insulating layer (20) on the carrier (12) with a molding compound (22). The first conductive layer is embedded in the first insulating layer (20). One or more of a plurality of bond pads (30), a plurality of conductive traces (32) and a plurality of microvias (56) are formed on the first conductive layer, the one or more of the bond pads (30), the conductive traces (32) and the microvias (56) formed on the first conductive layer defining a second conductive layer.Type: ApplicationFiled: January 21, 2014Publication date: December 3, 2015Inventors: Amlan SEN, Shoa-Siong Raymond LIM
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Publication number: 20140167240Abstract: The semiconductor device carrier comprises a conductive carrier, a dielectric layer, a conductive trace layer, a conductive stud layer and the plating conductive layer. The conductive carrier comprises at least one cavity. The dielectric layer has a first dielectric surface and a second dielectric surface opposite the first dielectric surface. The conductive trace layer disposes in the dielectric layer and is exposed on the second dielectric surface. The conductive stud layer disposes in the dielectric layer and is exposed on the first dielectric surface, wherein the conductive stud layer is electrically connected to the conductive trace layer. The plating conductive layer is disposed on the first dielectric surface and the exposed conductive stud layer. The cavity exposes the conductive trace layer and the dielectric layer.Type: ApplicationFiled: February 20, 2014Publication date: June 19, 2014Applicant: ADVANPACK SOLUTIONS PTE LTD.Inventors: Hwee-Seng Jimmy Chew, Kian-Hock LIM, Oviso Dominador Jr Fortaleza, Shoa-Siong Raymond Lim
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Patent number: 8709874Abstract: A conductive carrier having a first surface and a second surface is provided. The conductive trace layer is formed on the second surface of the conductive carrier. A conductive stud layer is formed on the conductive trace layer. A dielectric layer is formed on the conductive layer to encapsulate the conductive trace layer and the conductive stud layer. The conductive stud layer is exposed. A plating conductive layer is formed to envelop the conductive carrier, the dielectric layer and the exposed end of the conductive stud layer. A cavity is formed on the conductive carrier, wherein the conductive trace layer and the dielectric layer are exposed in the cavity. A surface finishing is formed on at least an exposed portion of the conductive stud layer. The plating conductive layer is removed.Type: GrantFiled: August 31, 2011Date of Patent: April 29, 2014Assignee: Advanpack Solutions Pte Ltd.Inventors: Hwee-Seng Jimmy Chew, Kian-Hock Lim, Oviso Dominador Jr Fortaleza, Shoa-Siong Raymond Lim
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Publication number: 20120058604Abstract: A conductive carrier having a first surface and a second surface is provided. The conductive trace layer is formed on the second surface of the conductive carrier. A conductive stud layer is formed on the conductive trace layer. A dielectric layer is formed on the conductive layer to encapsulate the conductive trace layer and the conductive stud layer. The conductive stud layer is exposed. A plating conductive layer is formed to envelop the conductive carrier, the dielectric layer and the exposed end of the conductive stud layer. A cavity is formed on the conductive carrier, wherein the conductive trace layer and the dielectric layer are exposed in the cavity. A surface finishing is formed on at least an exposed portion of the conductive stud layer. The plating conductive layer is removed.Type: ApplicationFiled: August 31, 2011Publication date: March 8, 2012Applicant: ADVANPACK SOLUTIONS PTE LTD.Inventors: Hwee-Seng Jimmy Chew, Kian-Hock Lim, Oviso Dominador Fortaleza, JR., Shoa-Siong Raymond Lim