Patents by Inventor Shoba Krishnan

Shoba Krishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10274451
    Abstract: This work provides an affordable approach for detecting environmental contaminants (e.g., arsenic in groundwater). Electro-chemical analysis of a sample is performed using a disposable three-electrode sensor that can be connected to an electrochemical analyzer (which is not disposable). The disposable sensor has a sample chamber to admit a liquid sample. The sensor includes a substrate disposed within the sample chamber that includes at least one conditioning reagent to condition the sample for electrochemical analysis. Analysis results can be displayed via a mobile device application.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: April 30, 2019
    Assignee: Santa Clara University
    Inventors: Unyoung Kim, Silvia Figueira, Shoba Krishnan
  • Publication number: 20160238555
    Abstract: This work provides an affordable approach for detecting environmental contaminants (e.g., arsenic in groundwater). Electro-chemical analysis of a sample is performed using a disposable three-electrode sensor that can be connected to an electrochemical analyzer (which is not disposable). The disposable sensor has a sample chamber to admit a liquid sample. The sensor includes a substrate disposed within the sample chamber that includes at least one conditioning reagent to condition the sample for electrochemical analysis. Analysis results can be displayed via a mobile device application.
    Type: Application
    Filed: February 18, 2016
    Publication date: August 18, 2016
    Inventors: Unyoung Kim, Silvia Figueira, Shoba Krishnan
  • Patent number: 5805089
    Abstract: A time-division data multiplexer has feedback for adjusting the select clock cross-over voltage. The multiplexer includes a multi-phase clock generator having a plurality of select clock outputs with different phases, a plurality of parallel data inputs and first and second serial data outputs. A first set of gating transistors is coupled between the first data output and a common node. Each transistor in the first set is gated by a corresponding data input and at least one corresponding select clock output. A second set of gating transistors is coupled between the second data output and the common node. Each transistor in the second set is gated by a corresponding data input and at least one corresponding select clock output. A first current source is coupled to the common node.
    Type: Grant
    Filed: October 21, 1996
    Date of Patent: September 8, 1998
    Assignee: LSI Logic Corporation
    Inventors: Alan S. Fiedler, Shoba Krishnan