Abstract: This document discloses systems and methods for implementing automatic test parameter tuning in constrained random verification. In aspects, a method receives a first set of parameters for testing a design under test, performs a first regression (e.g., an overnight regression test) on a design under test using the first set of parameters, and analyzes the results of the first regression including determining a coverage percentage. The method then generates an optimized set of parameters based on the analysis of the results of the first regression and performs an additional regression on the design under test using the optimized set of parameters. In aspects, the method is repeated using the optimized set of parameters until a coverage percentage is reached, or in some implementations, full coverage may be reached. Some implementations of the method utilize black-box optimization through use of a Bayesian optimization algorithm.

Abstract: Described herein are compositions and methods for treating cancer in a subject. Using the compositions and methods of the disclosure, a subject may be administered (i) an inhibitor and/or an overrider and (ii) a chemotherapeutic.

Abstract: Techniques message selection for hardware tracing in receiving system-on-chip (SoC) post-silicon debugging are described herein. An aspect includes receiving SoC design information corresponding to an SoC. Another aspect includes determining, based on the SoC design information, a set of messages that are exchanged between blocks of the SoC. Another aspect includes determining a set of possible combinations of messages of the set of messages. Another aspect includes determining a respective mutual information gain for each possible combination of messages in the set of possible combinations of messages. Another aspect includes selecting a combination of messages having a highest determined mutual information gain for monitoring via hardware tracing in the SoC.

Abstract: Compositions and methods for targeting chemoresistant cells in leukemia using combination therapies.

Abstract: A system is configured to generate assertions for verification of an integrated circuit hardware design expressed at a register transfer level (RTL) for variables of interest, each including an antecedent and a consequent. A relative importance score for the variables is determined by characterizing respective variables by a level of importance with respect to a target variable of the consequent. The relative importance scores may be combined to form a relative importance score of the assertion. A relative complexity score for the variable is determined by characterizing the variable by a level of understandability of the variable with respect to the target variable. The relative complexity scores are combined to form a relative complexity score of the assertion. The relative importance and complexity scores are combined to generate a rank score, which is used in ranking the assertion with respect to the RTL design for which the assertion was generated.

Abstract: A method of generating assertions for verification of a hardware design expressed at a register transfer level (RTL) includes running simulation traces through the design to generate simulation data; extract domain-specific information about the design for variables of interest; execute a data mining algorithm with the simulation data and the domain-specific information, to generate a set of candidate assertions for variable(s) of interest through machine learning with respect to the domain-specific information, the candidate assertions being likely invariants; conduct formal verification on the design with respect to each candidate assertion by outputting as invariants the candidate assertions that pass verification; iteratively feed back into the algorithm a counterexample trace generated by each failed candidate assertion, each counterexample trace including at least one additional variable in the design not previously input into the data mining algorithm, to thus increase coverage of a state space of the

Abstract: A system is configured to generate assertions for verification of an integrated circuit hardware design expressed at a register transfer level (RTL) for variables of interest, each including an antecedent and a consequent. A relative importance score for the variables is determined by characterizing respective variables by a level of importance with respect to a target variable of the consequent. The relative importance scores may be combined to form a relative importance score of the assertion. A relative complexity score for the variable is determined by characterizing the variable by a level of understandability of the variable with respect to the target variable. The relative complexity scores are combined to form a relative complexity score of the assertion. The relative importance and complexity scores are combined to generate a rank score, which is used in ranking the assertion with respect to the RTL design for which the assertion was generated.

Abstract: A method of generating assertions for verification of a hardware design expressed at a register transfer level (RTL) includes running simulation traces through the design to generate simulation data; extract domain-specific information about the design for variables of interest; execute a data mining algorithm with the simulation data and the domain-specific information, to generate a set of candidate assertions for variable(s) of interest through machine learning with respect to the domain-specific information, the candidate assertions being likely invariants; conduct formal verification on the design with respect to each candidate assertion by outputting as invariants the candidate assertions that pass verification; iteratively feed back into the algorithm a counterexample trace generated by each failed candidate assertion, each counterexample trace including at least one additional variable in the design not previously input into the data mining algorithm, to thus increase coverage of a state space of the