Patents by Inventor Shogo Itai

Shogo Itai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11985907
    Abstract: According to one embodiment, a magnetic memory device includes a magnetoresistance effect element including first and second magnetic layers each having a fixed magnetization direction, a third magnetic layer provided between the first and second magnetic layers, and having a variable magnetization direction, a first nonmagnetic layer between the first and third magnetic layers, and a second nonmagnetic layer between the second and third magnetic layers, and a switching element connected in series to the magnetoresistance effect element, changing from an electrically nonconductive state to an electrically conductive state when a voltage applied between two terminals is higher than or equal to a threshold voltage.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: May 14, 2024
    Assignee: Kioxia Corporation
    Inventors: Shogo Itai, Tadaomi Daibou, Yuichi Ito, Katsuyoshi Komatsu
  • Publication number: 20230189661
    Abstract: A switching element includes a first conductive layer, a second conductive layer, and a switching material layer provided between the first conductive layer and the second conductive layer and formed of an insulating material containing an additional element. The switching material layer includes a first interface region including a first interface between the first conductive layer and the switching material layer and a second interface region including a second interface between the second conductive layer and the switching material layer. A concentration of the additional element in the switching material layer has a first peak in the first interface region.
    Type: Application
    Filed: August 30, 2022
    Publication date: June 15, 2023
    Inventors: Shogo ITAI, Kazuya MATSUZAWA, Masahiko NAKAYAMA, Hiroyuki KANAYA, Hideyuki SUGIYAMA
  • Patent number: 11316097
    Abstract: According to one embodiment, a memory device includes a first wiring extending in a first direction, and a second wiring extending in a second direction that intersects the first direction. A memory cell is between the first wiring and the second wiring and includes a resistive memory element and a switching element that are connected in series between the first wiring and the second wiring. An insulating region surrounds side surfaces of the memory cell. The insulating region includes a first insulating part adjacent to a side surface of the resistive memory element and a second insulating part adjacent to a side surface of the switching element. The second insulating part has a higher thermal conductivity than the first insulating part.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: April 26, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Taichi Igarashi, Tadaomi Daibou, Junichi Ito, Tadashi Kai, Shogo Itai, Toshiyuki Enda
  • Publication number: 20220085277
    Abstract: According to one embodiment, a magnetic memory device includes a magnetoresistance effect element including first and second magnetic layers each having a fixed magnetization direction, a third magnetic layer provided between the first and second magnetic layers, and having a variable magnetization direction, a first nonmagnetic layer between the first and third magnetic layers, and a second nonmagnetic layer between the second and third magnetic layers, and a switching element connected in series to the magnetoresistance effect element, changing from an electrically nonconductive state to an electrically conductive state when a voltage applied between two terminals is higher than or equal to a threshold voltage.
    Type: Application
    Filed: March 15, 2021
    Publication date: March 17, 2022
    Applicant: Kioxia Corporation
    Inventors: Shogo ITAI, Tadaomi DAIBOU, Yuichi ITO, Katsuyoshi KOMATSU
  • Patent number: 11171175
    Abstract: According to one embodiment, a magnetic device includes a stacked body including a first magnetic layer, a second magnetic layer, and a non-magnetic layer between the first magnetic layer and the second magnetic layer. The stacked body has a quadrangular planar shape, the stacked body has a first side dimension in a first direction parallel to a surface of a substrate and a thickness in a second direction perpendicular to the surface of the substrate, and a ratio of the first side dimension to the thickness is in a range of 0.10 to 4.0.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: November 9, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tadashi Kai, Masahiko Nakayama, Jyunichi Ozeki, Shogo Itai
  • Publication number: 20210296568
    Abstract: According to one embodiment, a memory device includes a first wiring extending in a first direction, and a second wiring extending in a second direction that intersects the first direction. A memory cell is between the first wiring and the second wiring and includes a resistive memory element and a switching element that are connected in series between the first wiring and the second wiring. An insulating region surrounds side surfaces of the memory cell. The insulating region includes a first insulating part adjacent to a side surface of the resistive memory element and a second insulating part adjacent to a side surface of the switching element. The second insulating part has a higher thermal conductivity than the first insulating part.
    Type: Application
    Filed: August 26, 2020
    Publication date: September 23, 2021
    Inventors: Taichi IGARASHI, Tadaomi DAIBOU, Junichi ITO, Tadashi KAI, Shogo ITAI, Toshiyuki ENDA
  • Publication number: 20210296585
    Abstract: A switching device in an embodiment includes: a first electrode; a second electrode, and a switching layer disposed between the first electrode and the second electrode. The switching layer is made of a material containing hafnium nitride. Otherwise, the switching layer is made of a material containing bismuth and at least one selected from the group consisting of silicon oxide, aluminum oxide, zirconium oxide, and gallium oxide, or a material containing at least one selected from the group consisting of bismuth oxide, bismuth nitride, bismuth boride, and bismuth sulfide.
    Type: Application
    Filed: September 14, 2020
    Publication date: September 23, 2021
    Applicant: Kioxia Corporation
    Inventors: Tadaomi DAIBOU, Hiroki KAWAI, Katsuyoshi KOMATSU, Weidong LI, Shogo ITAI, Kouji MATSUO
  • Publication number: 20200302984
    Abstract: According to one embodiment, a magnetic device includes a stacked body including a first magnetic layer, a second magnetic layer, and a non-magnetic layer between the first magnetic layer and the second magnetic layer. The stacked body has a quadrangular planar shape, the stacked body has a first side dimension in a first direction parallel to a surface of a substrate and a thickness in a second direction perpendicular to the surface of the substrate, and a ratio of the first side dimension to the thickness is in a range of 0.10 to 4.0.
    Type: Application
    Filed: August 30, 2019
    Publication date: September 24, 2020
    Inventors: Tadashi KAI, Masahiko NAKAYAMA, Jyunichi OZEKI, Shogo ITAI
  • Patent number: 10707356
    Abstract: According to one embodiment, a magnetic memory device includes a stacked structure including first and second magnetic layers having variable and fixed magnetization directions, respectively, and a nonmagnetic layer provided between the first and second magnetic layers and containing a first compound containing first cationic and anionic elements, and a predetermined-material layer provided around side surfaces of the stacked structure and containing a second compound containing second added cationic and second added anionic elements. An absolute value of a valence number (ionic valency) of the second added cationic element is less than that of the first cationic element, and an absolute value of a valence number (ionic valency) of the second added anionic element is less than that of the first anionic element.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: July 7, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Megumi Yakabe, Yasushi Nakasaki, Tadaomi Daibou, Tadashi Kai, Junichi Ito, Masahiro Koike, Shogo Itai, Takamitsu Ishihara
  • Publication number: 20200083289
    Abstract: According to one embodiment, a magnetic memory device includes a stacked structure including first and second magnetic layers having variable and fixed magnetization directions, respectively, and a nonmagnetic layer provided between the first and second magnetic layers and containing a first compound containing first cationic and anionic elements, and a predetermined-material layer provided around side surfaces of the stacked structure and containing a second compound containing second added cationic and second added anionic elements. An absolute value of a valence number (ionic valency) of the second added cationic element is less than that of the first cationic element, and an absolute value of a valence number (ionic valency) of the second added anionic element is less than that of the first anionic element.
    Type: Application
    Filed: March 14, 2019
    Publication date: March 12, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Megumi YAKABE, Yasushi NAKASAKI, Tadaomi DAIBOU, Tadashi KAI, Junichi ITO, Masahiro KOIKE, Shogo ITAI, Takamitsu ISHIHARA
  • Publication number: 20190096461
    Abstract: According to one embodiment, a memory device includes: a first memory element arranged above a substrate; a first contact portion adjacent to the first memory element in a first direction parallel to a surface of the substrate; a second contact portion arranged above the first memory element in a second direction perpendicular to the surface of the substrate; and a second memory element arranged above the first contact portion in the second direction. First dimensions at upper parts of the first and second memory elements are smaller than second dimensions at lower parts of the first and second memory elements, and third dimensions at upper parts of the first and second contact portions are larger than fourth dimensions at lower parts of the first and second contact portions.
    Type: Application
    Filed: March 9, 2018
    Publication date: March 28, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Masahiro Koike, Shogo Itai, Tadaomi Daibou, Chikayoshi Kamata, Junichi Ito, Masahiko Nakayama
  • Patent number: 9935260
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic layer, a second magnetic layer, a third magnetic layer, and a first non-magnetic layer. The third magnetic layer is provided between a first part of the first magnetic layer and the second magnetic layer. The first non-magnetic layer is provided between the second magnetic layer and the third magnetic layer. The first magnetic layer further includes a second part. At least a portion of the second part overlaps at least a portion of the third magnetic layer in a second direction orthogonal to a first direction from the first part toward the second magnetic layer.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: April 3, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Saida, Shogo Itai, Chikayoshi Kamata
  • Patent number: 9805780
    Abstract: A nonvolatile memory of an embodiment includes: first through fifth wirings; and a memory cell including: a first circuit including a first magnetoresistive element and a first select transistor, the first magnetoresistive element and the first select transistor being electrically connected in series, the first magnetoresistive element including a first reference layer, a first storage layer, and a first nonmagnetic layer between the first reference layer and the first storage layer; a second circuit including a second magnetoresistive element and a second select transistor, the second magnetoresistive element and the second select transistor being electrically connected in series, the second magnetoresistive element including a second reference layer, a second storage layer, and a second nonmagnetic layer between the second reference layer and the second storage layer; a third circuit including first and second transistors; and a fourth circuit including third and fourth transistors.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: October 31, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shogo Itai, Hiroki Noguchi
  • Publication number: 20170279037
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic layer, a second magnetic layer, a third magnetic layer, and a first non-magnetic layer. The third magnetic layer is provided between a first part of the first magnetic layer and the second magnetic layer. The first non-magnetic layer is provided between the second magnetic layer and the third magnetic layer. The first magnetic layer further includes a second part. At least a portion of the second part overlaps at least a portion of the third magnetic layer in a second direction orthogonal to a first direction from the first part toward the second magnetic layer.
    Type: Application
    Filed: September 14, 2016
    Publication date: September 28, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Daisuke SAIDA, Shogo ITAI, Chikayoshi KAMATA
  • Publication number: 20170160406
    Abstract: A photodetector according to an embodiment includes; at least one photodiode including: a first electrode; an n-type semiconductor layer disposed on the first electrode; a first p-type semiconductor layer disposed above the n-type semiconductor layer, the first p-type semiconductor layer including a first surface region and a second surface region; a second p-type semiconductor layer disposed in the first surface region of the first p-type semiconductor layer, the second p-type semiconductor layer having a higher p-type impurity concentration than the first p-type semiconductor layer; and a second electrode disposed on the second surface region of the first p-type semiconductor layer and on the second p-type semiconductor layer.
    Type: Application
    Filed: February 16, 2017
    Publication date: June 8, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: KAZUYA MATSUZAWA, SHOGO ITAI, TAKAMITSU ISHIHARA
  • Publication number: 20170103792
    Abstract: A nonvolatile memory of an embodiment includes: first through fifth wirings; and a memory cell including: a first circuit including a first magnetoresistive element and a first select transistor, the first magnetoresistive element and the first select transistor being electrically connected in series, the first magnetoresistive element including a first reference layer, a first storage layer, and a first nonmagnetic layer between the first reference layer and the first storage layer; a second circuit including a second magnetoresistive element and a second select transistor, the second magnetoresistive element and the second select transistor being electrically connected in series, the second magnetoresistive element including a second reference layer, a second storage layer, and a second nonmagnetic layer between the second reference layer and the second storage layer; a third circuit including first and second transistors; and a fourth circuit including third and fourth transistors.
    Type: Application
    Filed: September 16, 2016
    Publication date: April 13, 2017
    Inventors: Shogo Itai, Hiroki Noguchi