Patents by Inventor Shogo Kiyota

Shogo Kiyota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7005673
    Abstract: An ITO film-formed substrate having excellent alkali resistance and adhesion is provided. For the ITO film-formed substrate, a structure is adopted in which a color filter 102, an organic protective film 103, intermediate layers 104a and 104b, and an ITO film 105 having an electrode pattern patterned therein are formed in this order from the bottom upwards on a surface of a glass substrate 101. The intermediate layer 104a is deposited on a surface of the organic protective film 103 through a high-frequency sputtering method using Ar as an introduced gas, and is made of a metal oxide that is not prone to dissolving in alkalis; the intermediate layer 104b is deposited through a reactive sputtering method or a high-frequency sputtering method, and is made of a metal oxide or metal nitride that is not prone to dissolving in alkalis.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: February 28, 2006
    Assignee: Nippon Sheet Glass Co., Ltd.
    Inventors: Shogo Kiyota, Yukihiro Katoh
  • Publication number: 20040227885
    Abstract: An ITO film-formed substrate having excellent alkali resistance and adhesion is provided. For the ITO film-formed substrate, a structure is adopted in which a color filter 102, an organic protective film 103, intermediate layers 104a and 104b, and an ITO film 105 having an electrode pattern patterned therein are formed in this order from the bottom upwards on a surface of a glass substrate 101. The intermediate layer 104a is deposited on a surface of the organic protective film 103 through a high-frequency sputtering method using Ar as an introduced gas, and is made of a metal oxide that is not prone to dissolving in alkalis; the intermediate layer 104b is deposited through a reactive sputtering method or a high-frequency sputtering method, and is made of a metal oxide or metal nitride that is not prone to dissolving in alkalis.
    Type: Application
    Filed: January 9, 2004
    Publication date: November 18, 2004
    Inventors: Shogo Kiyota, Yukihiro Katoh
  • Publication number: 20040229465
    Abstract: An organic EL device 10 is comprised of an ITO film-formed substrate 4 that is comprised of a glass substrate 1, an SiO2 film 2 that is formed on a surface of the glass substrate 1 and is for alkaline passivation, and an ITO film 3 that is formed on the surface of the SiO2 film 2, a hole transport layer 5 that is formed on the surface of the ITO film 3 and is for efficiently injecting holes into a light-emitting layer 6, a thin metallic film layer 7 that is formed on the light-emitting layer 6 and is for injecting electrons into the light-emitting layer 6, and the light-emitting layer 6 which emits light upon recombination of the injected holes and electrons. The surface smoothness of the glass substrate 1 is controlled to satisfy 0 nm≦Rz≦4 nm. As a result, non-luminescent spots do not occur and hence durability can be improved.
    Type: Application
    Filed: December 4, 2003
    Publication date: November 18, 2004
    Applicant: Nippon Sheet Glass Co., Ltd.
    Inventors: Shogo Kiyota, Shunji Wada, Yukihiro Katoh, Naoki Kinugasa
  • Patent number: 6815761
    Abstract: In the semiconductor integrated circuit device, an AND-type flash memory is formed on a substrate in which stripe-like element separation regions 5 are formed and active regions L sandwiched between the element separation regions 5 are formed like stripes. A silicon monocrystal substrate containing nitrogen or carbon is used as the semiconductor substrate, to reduce dislocation defects and junction leakages so that the reliability and yield are improved.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: November 9, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Toshiaki Nishimoto, Takashi Aoyagi, Shogo Kiyota
  • Publication number: 20040219727
    Abstract: Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer. The well region is formed with the gate insulating films of MIS•FETs.
    Type: Application
    Filed: June 7, 2004
    Publication date: November 4, 2004
    Inventors: Hiroto Kawagoe, Tatsumi Shirasu, Shogo Kiyota, Norio Suzuki, Eiichi Yamada, Yuji Sugino, Manabu Kitano, Yoshihiko Sakurai, Takashi Naganuma, Hisashi Arakawa
  • Patent number: 6806130
    Abstract: Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer. The well region is formed with the gate insulating films of MIS·FETs.
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: October 19, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Hiroto Kawagoe, Tatsumi Shirasu, Shogo Kiyota, Norio Suzuki, Eiichi Yamada, Yuji Sugino, Manabu Kitano, Yoshihiko Sakurai, Takashi Naganuma, Hisashi Arakawa
  • Patent number: 6685805
    Abstract: In a method of manufacturing a substrate having a transparent conductive film in which sputtering is carried out on a transparent insulating substrate using an indium oxide/tin oxide target under an atmosphere of a mixed gas containing argon and oxygen, when the ratio of oxygen to argon in the mixed gas is in a suitable range of 0.016 to 0.018, the carrier density of the transparent conductive film becomes a maximum, while the mobility rises progressively as the ratio of oxygen to argon increases. The surface resistance of the transparent conductive film, that is the reciprocal of the product of the carrier density and the mobility, 1/(carrier density×mobility), takes a minimum value when the ratio of oxygen to argon is in the above suitable range. In this case, crystallization of the film is promoted and the percentage change between the surface resistance of the film before heat treatment and the surface resistance of the film after heat treatment can be kept down to within ±10%.
    Type: Grant
    Filed: July 20, 2001
    Date of Patent: February 3, 2004
    Assignee: Nippon Sheet Glass Co., Ltd.
    Inventors: Shogo Kiyota, Yukihiro Katoh
  • Publication number: 20030205731
    Abstract: In the semiconductor integrated circuit device, an AND-type flash memory is formed on a substrate in which stripe-like element separation regions 5 are formed and active regions L sandwiched between the element separation regions 5 are formed like stripes. A silicon monocrystal substrate containing nitrogen or carbon is used as the semiconductor substrate, to reduce dislocation defects and junction leakages so that the reliability and yield are improved.
    Type: Application
    Filed: April 22, 2003
    Publication date: November 6, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Toshiaki Nishimoto, Takashi Aoyagi, Shogo Kiyota
  • Patent number: 6630375
    Abstract: Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer. The well region is formed with the gate insulating films of MIS·FETs.
    Type: Grant
    Filed: December 5, 2001
    Date of Patent: October 7, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Hiroto Kawagoe, Tatsumi Shirasu, Shogo Kiyota, Norio Suzuki, Eiichi Yamada, Yuji Sugino, Manabu Kitano, Yoshihiko Sakurai, Takashi Naganuma, Hisashi Arakawa
  • Patent number: 6583467
    Abstract: In the semiconductor integrated circuit device, an AND-type flash memory is formed on a substrate in which stripe-like element separation regions 5 are formed and active regions L sandwiched between the element separation regions 5 are formed like stripes. A silicon monocrystal substrate containing nitrogen or carbon is used as the semiconductor substrate, to reduce dislocation defects and junction leakages so that the reliability and yield are improved.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: June 24, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Toshiaki Nishimoto, Takashi Aoyagi, Shogo Kiyota
  • Publication number: 20020173091
    Abstract: In the semiconductor integrated circuit device, an AND-type flash memory is formed on a substrate in which stripe-like element separation regions 5 are formed and active regions L sandwiched between the element separation regions 5 are formed like stripes. A silicon monocrystal substrate containing nitrogen or carbon is used as the semiconductor substrate, to reduce dislocation defects and junction leakages so that the reliability and yield are improved.
    Type: Application
    Filed: June 26, 2002
    Publication date: November 21, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Toshiaki Nishimoto, Takashi Aoyagi, Shogo Kiyota
  • Patent number: 6444514
    Abstract: In the semiconductor integrated circuit device, an AND-type flash memory is formed on a substrate in which stripe-like element separation regions 5 are formed and active regions L sandwiched between the element separation regions 5 are formed like stripes. A silicon monocrystal substrate containing nitrogen or carbon is used as the semiconductor substrate, to reduce dislocation defects and junction leakages so that the reliability and yield are improved.
    Type: Grant
    Filed: October 3, 2000
    Date of Patent: September 3, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Toshiaki Nishimoto, Takashi Aoyagi, Shogo Kiyota
  • Publication number: 20020061615
    Abstract: Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer The well region is formed with the gate insulating films of MIS·FETs.
    Type: Application
    Filed: December 14, 2001
    Publication date: May 23, 2002
    Inventors: Hiroto Kawagoe, Tatsumi Shirasu, Shogo Kiyota, Norio Suzuki, Eiichi Yamada, Yuji Sugino, Manabu Kitano, Yoshihiko Sakurai, Takashi Naganuma, Hisashi Arakawa
  • Publication number: 20020055204
    Abstract: Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer. The well region is formed with the gate insulating films of MIS.FETS.
    Type: Application
    Filed: December 5, 2001
    Publication date: May 9, 2002
    Inventors: Hiroto Kawagoe, Tatsumi Shirasu, Shogo Kiyota, Norio Suzuki, Eiichi Yamada, Yuji Sugino, Manabu Kitano, Yoshihiko Sakurai, Takashi Naganuma, Hisashi Arakawa
  • Patent number: 6368905
    Abstract: Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer. The well region is formed with the gate insulating films of MIS.FETs.
    Type: Grant
    Filed: February 25, 2000
    Date of Patent: April 9, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Hiroto Kawagoe, Tatsumi Shirasu, Shogo Kiyota, Norio Suzuki, Eiichi Yamada, Yuji Sugino, Manabu Kitano, Yoshihiko Sakurai, Takashi Naganuma, Hisashi Arakawa
  • Publication number: 20020034836
    Abstract: In a method of manufacturing a substrate having a transparent conductive film in which sputtering is carried out on a transparent insulating substrate using an indium oxide/tin oxide target under an atmosphere of a mixed gas containing argon and oxygen, when the ratio of oxygen to argon in the mixed gas is in a suitable range of 0.016 to 0.018, the carrier density of the transparent conductive film becomes a maximum, while the mobility rises progressively as the ratio of oxygen to argon increases. The surface resistance of the transparent conductive film, that is the reciprocal of the product of the carrier density and the mobility, 1/(carrier density×mobility), takes a minimum value when the ratio of oxygen to argon is in the above suitable range. In this case, crystallization of the film is promoted and the percentage change between the surface resistance of the film before heat treatment and the surface resistance of the film after heat treatment can be kept down to within ±10%.
    Type: Application
    Filed: July 20, 2001
    Publication date: March 21, 2002
    Applicant: Nippon Sheet Glass Co., Ltd.
    Inventors: Shogo Kiyota, Yukihiro Katoh
  • Patent number: 6043114
    Abstract: Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer. The well region is formed with the gate insulating films of MIS.FETs.
    Type: Grant
    Filed: September 22, 1997
    Date of Patent: March 28, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Hiroto Kawagoe, Tatsumi Shirasu, Shogo Kiyota, Norio Suzuki, Eiichi Yamada, Yuji Sugino, Manabu Kitano, Yoshihiko Sakurai, Takashi Naganuma, Hisashi Arakawa