Abstract: In a gradient direction calculation device, an element gradient vector calculation unit calculates two mutually perpendicular element gradient vectors with respect to a pixel of interest by using a difference in pixel values in the vicinity of the pixel of interest. A quadrant determination unit determines, based on a combination of positive/negative signs of each of the two element gradient vectors, a quadrant among the four quadrants defined by the two element gradient vectors that contains a gradient direction of the pixel of interest. A ratio comparison unit determines comparison results by comparing each of the ratios of magnitudes of the two element gradient vectors with a predetermined threshold. A gradient direction determination unit determines a gradient direction corresponding to a combination of the positive/negative signs and the comparison results.

Abstract: In a gradient direction calculation device, an element gradient vector calculation unit calculates two mutually perpendicular element gradient vectors with respect to a pixel of interest by using a difference in pixel values in the vicinity of the pixel of interest. A quadrant determination unit determines, based on a combination of positive/negative signs of each of the two element gradient vectors, a quadrant among the four quadrants defined by the two element gradient vectors that contains a gradient direction of the pixel of interest. A ratio comparison unit determines comparison results by comparing each of the ratios of magnitudes of the two element gradient vectors with a predetermined threshold. A gradient direction determination unit determines a gradient direction corresponding to a combination of the positive/negative signs and the comparison results.

Abstract: A SIMD processor with a versatile hardware configuration performs efficient range determination that is frequently used in image processing and recognition. A SIMD processor includes a range determination arithmetic unit including first and second registers that can store two values. The SIMD processor uses three values, namely, these two values and the value of source data input from a register file unit, to flexibly set the processing target data for range determination and the two boundaries defining the processing target range of the range determination.

Abstract: A very long instruction word (VLIW) processor that performs efficient processing including extended bits operations is provided. The VLIW processor includes an instruction control unit, a register file unit, and an instruction execution unit. The instruction execution unit includes a plurality of slots, and a state register arranged between the second slot and the third slot to transfer N-bit data between the second and third slots. The VLIW processor stores data output from the third slot into the state register and uses the data, and thus achieves efficient processing including bit-expanded operations, such as processing performed in response to instructions commonly used in image processing, image recognition, and other processing, while preventing scaling up of the circuit.

Abstract: Provided is an information processing device including an instruction cache, a data cache, first and second arithmetic unit groups including a plurality of arithmetic units capable of parallel operation, a first arithmetic-control circuit that generates one or more operation instructions for the first arithmetic unit group, and a second arithmetic-control circuit that generates one or more operation instructions for the second arithmetic unit group based on an instruction code of a fixed instruction register. The first arithmetic unit group sets the instruction code to the fixed instruction register according to an operation instruction generated based on a first specific instruction code by the first arithmetic-control circuit, and provides data to the second arithmetic unit group according to an operation instruction generated based on a second specific instruction code by the first arithmetic-control circuit.

Abstract: A semiconductor device of the present invention has processor elements each of which divides data that is contiguous in one direction into multiple data groups and processes them, a processor element control unit that issues a data shift instruction, and a data transfer network that performs data transfer between adjacent processor elements. The processor elements each have a data storage unit that stores one of the multiple data groups, a data selector that outputs transfer data obtained by selecting either of head data or end data of one data group according to a data shift instruction into a data transfer network, a data shifter that shifts a position at which the data group is stored to the right or to the left according to the data shift instruction, and a data connector that connects the data group which is shifted and the transfer data obtained through the data transfer network.

Abstract: In a human detection device 1, an edge extractor 11 carries out edge extraction processing to an input image 21 and produces a horizontal edge image 22. A shoulder detector 12 detects a shoulder center and a shoulder width of a person included in the input image 21. A foot detector 13 detects a foot position of the person based on the detected shoulder center and shoulder width. A top detector 14 detects a top position of the person based on the detected shoulder center and shoulder width. A size determiner 15 determines a horizontal size of the person based on the detected shoulder width and determines a vertical size of the person based on the detected foot position and top position. The size determiner 15 produces human range data 28 including the determined sizes, the shoulder center position, the foot position, and the top position.

Abstract: An object detection apparatus, a program, and an integrated circuit enable the contour of an object to be detected in an appropriate manner in an image including an object and its background with almost no contrast between them in a predetermined direction of the image. A vertical direction edge extraction filter in a filtering unit extracts, from an input image, a contour component in a first direction (e.g., vertical direction) of the image. A horizontal direction continuity detection unit in the filtering unit detects, in a second direction (e.g., horizontal direction) perpendicular to the first direction, the continuity of the contour component extracted by the vertical direction edge extraction filter. An object area detection unit detects (estimates) the contour of the object in the image based on the continuity of the contour component in the second direction (e.g., horizontal direction) detected by the horizontal direction continuity detection unit.

Abstract: A very long instruction word (VLIW) processor performs efficient processing including extended bits operations, such as processing performed in response to instructions commonly used in image processing, image recognition, and other processing, while preventing scaling up of the circuit. The VLIW processor includes an instruction control unit, a register file unit, and an instruction execution unit. The instruction execution unit includes a plurality of slots, and a state register arranged between the second slot and the third slot to transfer N-bit data between the second and third slots. The VLIW processor stores data output from the third slot into the state register and uses the data, and thus achieves efficient processing including bit-expanded operations, such as processing performed in response to instructions commonly used in image processing, image recognition, and other processing, while preventing scaling up of the circuit.

Abstract: A SIMD processor with a versatile hardware configuration performs efficient range determination that is frequently used in image processing and recognition. A SIMD processor includes a range determination arithmetic unit including first and second registers that can store two values. The SIMD processor uses three values, namely, these two values and the value of source data input from a register file unit, to flexibly set the processing target data for range determination and the two boundaries defining the processing target range of the range determination.

Abstract: It is an object of the present invention to achieve an object detection apparatus, a program, and an integrated circuit each of which is capable of appropriately detecting an axially symmetric object in an image, whatever image is to be processed, without performing any complicated thresholding. The object detection apparatus includes a processing object region determination unit, a variance acquisition unit, a matching determination unit, and an object region detection unit. The processing object region determination unit sets a symmetry axis in an image region included in an image and divides the image region into a determination image region and a reference image region so as to be line symmetric with respect to the symmetry axis. The variance acquisition unit acquires a degree of variance of image feature amount in the image region.

Abstract: In a human detection device 1, an edge extractor 11 carries out edge extraction processing to an input image 21 and produces a horizontal edge image 22. A shoulder detector 12 detects a shoulder center and a shoulder width of a person included in the input image 21. A foot detector 13 detects a foot position of the person based on the detected shoulder center and shoulder width. A top detector 14 detects a top position of the person based on the detected shoulder center and shoulder width. A size determiner 15 determines a horizontal size of the person based on the detected shoulder width and determines a vertical size of the person based on the detected foot position and top position. The size determiner 15 produces human range data 28 including the determined sizes, the shoulder center position, the foot position, and the top position.

Abstract: It is an object of the present invention to achieve an object detection apparatus, a program, and an integrated circuit each of which is capable of appropriately detecting an axially symmetric object in an image, whatever image is to be processed, without performing any complicated thresholding. The object detection apparatus includes a processing object region determination unit, a variance acquisition unit, a matching determination unit, and an object region detection unit. The processing object region determination unit sets a symmetry axis in an image region included in an image and divides the image region into a determination image region and a reference image region so as to be line symmetric with respect to the symmetry axis. The variance acquisition unit acquires a degree of variance of image feature amount in the image region.

Abstract: An object detection apparatus, a program, and an integrated circuit enable the contour of an object to be detected in an appropriate manner in an image including an object and its background with almost no contrast between them in a predetermined direction of the image. A vertical direction edge extraction filter in a filtering unit extracts, from an input image, a contour component in a first direction (e.g., vertical direction) of the image. A horizontal direction continuity detection unit in the filtering unit detects, in a second direction (e.g., horizontal direction) perpendicular to the first direction, the continuity of the contour component extracted by the vertical direction edge extraction filter. An object area detection unit detects (estimates) the contour of the object in the image based on the continuity of the contour component in the second direction (e.g., horizontal direction) detected by the horizontal direction continuity detection unit.

Abstract: A VLIW processor executes a very long instruction word containing a plurality of instructions, and executes a plurality of instruction streams at low cost. A processor executing a very long instruction word containing a plurality of instructions fetches concurrently the very long instruction words of up to M instruction streams, from N instruction caches including a plurality of memory banks to store the very long instruction words of the M instruction streams.

Abstract: A processor has a plurality of PEs (processing elements) that operate in parallel based on operation commands and an information collection unit that collects the data of the plurality of PEs, wherein each of the plurality of PEs holds data and a condition flag, supplies the data and the condition flag to the information collection unit upon receiving an operation command, and upon receiving an update request for updating the condition flag, updates the condition flag in accordance with the update request that was received; and the information collection unit, upon receiving the data and the condition flags, selects one PE based on a predetermined order of priority from among the PEs for which the received condition flags are active and both supplies the data of the selected PE as collection result data and supplies an update request for updating the condition flag of the PE that was selected.

Abstract: A semiconductor device of the present invention has processor elements each of which divides data that is contiguous in one direction into multiple data groups and processes them, a processor element control unit that issues a data shift instruction, and a data transfer network that performs data transfer between adjacent processor elements. The processor elements each have a data storage unit that stores one of the multiple data groups, a data selector that outputs transfer data obtained by selecting either of head data or end data of one data group according to a data shift instruction into a data transfer network, a data shifter that shifts a position at which the data group is stored to the right or to the left according to the data shift instruction, and a data connector that connects the data group which is shifted and the transfer data obtained through the data transfer network.

Abstract: In an information processing device for processing VLIW includes memory banks, a memory banks are used to store an instruction word group constituting a very-long instruction. A program counter outputs an instruction address indicating a head memory bank containing a head part of the very long instruction of the next cycle. A memory bank control device uses information regarding the instruction address for the very long instruction and the number of memory banks associated with the very long instruction to specify the use memory bank to be used in the next cycle and the nonuse memory bank not to be used in the next cycle. The memory bank control device controls the operation of the nonuse memory bank. The instruction decoder decodes the very long instruction fetched from the use memory bank. An arithmetic device executes the decoded very long instruction.

Abstract: Provided is an information processing device including an instruction cache, a data cache, first and second arithmetic unit groups including a plurality of arithmetic units capable of parallel operation, a first arithmetic-control circuit that generates one or more operation instructions for the first arithmetic unit group, and a second arithmetic-control circuit that generates one or more operation instructions for the second arithmetic unit group based on an instruction code of a fixed instruction register. The first arithmetic unit group sets the instruction code to the fixed instruction register according to an operation instruction generated based on a first specific instruction code by the first arithmetic-control circuit, and provides data to the second arithmetic unit group according to an operation instruction generated based on a second specific instruction code by the first arithmetic-control circuit.

Abstract: A processor has a plurality of PEs (processing elements) that operate in parallel based on operation commands and an information collection unit that collects the data of the plurality of PEs, wherein each of the plurality of PEs holds data and a condition flag, supplies the data and the condition flag to the information collection unit upon receiving an operation command, and upon receiving an update request for updating the condition flag, updates the condition flag in accordance with the update request that was received; and the information collection unit, upon receiving the data and the condition flags, selects one PE based on a predetermined order of priority from among the PEs for which the received condition flags are active and both supplies the data of the selected PE as collection result data and supplies an update request for updating the condition flag of the PE that was selected.