Abstract: A DRAM is constructed by a memory section, a multiplexer (MPX), an inverting circuit and a non-inverting circuit. The memory section stores data transferred through a data bus. The multiplexer selects a width of the data bus based on a mode signal for designating the bus width. The mode signal is shown by a MODE0 signal. The inverting circuit inverts writing data and/or reading data based on a mode signal for designating inversion of data. This mode signal is shown by a MODE1 signal. The non-inverting circuit stops transmission of non-inverted data at an inverting time and passes or transmits data at a non-inverting time on the basis of the MODE1 signal. In this structure, a plurality of access methods can be used with respect to a single DRAM so that extendability of the DRAM is improved and a high speed access operation is performed.