Patents by Inventor Shoichi KUGA

Shoichi KUGA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11256171
    Abstract: A film resist is a member for being bonded to a main surface of a substrate, which main surface is provided with a mark. The film resist includes a cutout for the mark to be checked.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: February 22, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroyuki Nakamura, Shinya Soneda, Shoichi Kuga
  • Patent number: 11145712
    Abstract: A semiconductor apparatus includes a power semiconductor device, a resin film and a sealing insulating material. The power semiconductor device includes: a first electrode covering a first region on one main surface of the semiconductor substrate; a second electrode formed on the other main surface of the semiconductor substrate; a guard ring formed in a second region outer than the first region; and a non-conductive inorganic film located in the second region and covering the guard ring. The resin film overlaps the guard ring in a plan view, and the resin film on the non-conductive inorganic film has a thickness of 35 ?m or more. The resin film is a film of a single layer, and the resin film has an outermost edge in the form of a downwardly spreading fillet. The outermost edge of the resin film is inner than an outermost edge of the semiconductor substrate.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: October 12, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Tetsu Negishi, Shoichi Kuga
  • Publication number: 20200058733
    Abstract: A semiconductor apparatus includes a power semiconductor device, a resin film and a sealing insulating material. The power semiconductor device includes: a first electrode covering a first region on one main surface of the semiconductor substrate; a second electrode formed on the other main surface of the semiconductor substrate; a guard ring formed in a second region outer than the first region; and a non-conductive inorganic film located in the second region and covering the guard ring. The resin film overlaps the guard ring in a plan view, and the resin film on the non-conductive inorganic film has a thickness of 35 ?m or more. The resin film is a film of a single layer, and the resin film has an outermost edge in the form of a downwardly spreading fillet. The outermost edge of the resin film is inner than an outermost edge of the semiconductor substrate.
    Type: Application
    Filed: April 24, 2017
    Publication date: February 20, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tetsu NEGISHI, Shoichi KUGA
  • Patent number: 10468314
    Abstract: A semiconductor power module includes: an insulating substrate including a concave portion provided on a top surface of the insulating substrate; a substrate electrode embedded in the concave portion; a semiconductor device bonded onto the substrate electrode; and an insulating resin covering a top end part of the substrate electrode.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: November 5, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventor: Shoichi Kuga
  • Publication number: 20190243245
    Abstract: A film resist is a member for being bonded to a main surface of a substrate, which main surface is provided with a mark. The film resist includes a cutout for the mark to be checked.
    Type: Application
    Filed: November 2, 2018
    Publication date: August 8, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hiroyuki NAKAMURA, Shinya SONEDA, Shoichi KUGA
  • Patent number: 10073360
    Abstract: An edge exposure apparatus for exposure of an outer circumferential portion of a semiconductor substrate to light includes a light source provided to be able to emit light to the outer circumferential portion and a mirror having a reflection surface arranged to extend in a direction intersecting with an optical axis of light emitted from the light source. The mirror is provided between the outer circumferential portion and a center of the semiconductor substrate in a radial direction of the semiconductor substrate in exposure of the outer circumferential portion of the semiconductor substrate to light.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: September 11, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Naoyuki Takeda, Shoichi Kuga
  • Publication number: 20180254228
    Abstract: A semiconductor power module includes: an insulating substrate including a concave portion provided on a top surface of the insulating substrate; a substrate electrode embedded in the concave portion; a semiconductor device bonded onto the substrate electrode; and an insulating resin covering a top end part of the substrate electrode.
    Type: Application
    Filed: October 23, 2017
    Publication date: September 6, 2018
    Applicant: Mitsubishi Electric Corporation
    Inventor: Shoichi KUGA
  • Patent number: 9899189
    Abstract: A technique disclosed in the present specification relates to an ion implanter capable of preventing a semiconductor substrate from being damaged by an abnormal electric discharge through a simple method. The ion implanter of this technique includes an ion irradiation unit configured to irradiate a surface of a semiconductor substrate with ions. The ion implanter also includes at least one electrode (needle electrode, annular electrode) disposed in a position in the vicinity of at least one of back and side surfaces of an end of the semiconductor substrate. The position is dischargeable to and from the semiconductor substrate. The at least one electrode (needle electrode, annular electrode) is spaced apart from the semiconductor substrate.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: February 20, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventor: Shoichi Kuga
  • Publication number: 20180024437
    Abstract: An edge exposure apparatus for exposure of an outer circumferential portion of a semiconductor substrate to light includes a light source provided to be able to emit light to the outer circumferential portion and a mirror having a reflection surface arranged to extend in a direction intersecting with an optical axis of light emitted from the light source. The mirror is provided between the outer circumferential portion and a center of the semiconductor substrate in a radial direction of the semiconductor substrate in exposure of the outer circumferential portion of the semiconductor substrate to light.
    Type: Application
    Filed: January 28, 2015
    Publication date: January 25, 2018
    Applicant: Mitsubishi Electric Corporation
    Inventors: Naoyuki TAKEDA, Shoichi KUGA
  • Patent number: 9760007
    Abstract: A semiconductor device manufacturing method of the present invention includes a coating step of coating a front surface of a wafer with a material containing a solvent, a volatilization step of volatilizing the solvent by heating the material, and a rinse step of jetting an edge rinse solution for removing the material from a first nozzle to a peripheral portion of the front surface of the wafer while rotating the wafer.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: September 12, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventor: Shoichi Kuga
  • Publication number: 20170207080
    Abstract: A semiconductor device manufacturing method of the present invention includes a coating step of coating a front surface of a wafer with a material containing a solvent, a volatilization step of volatilizing the solvent by heating the material, and a rinse step of jetting an edge rinse solution for removing the material from a first nozzle to a peripheral portion of the front surface of the wafer while rotating the wafer.
    Type: Application
    Filed: February 13, 2014
    Publication date: July 20, 2017
    Applicant: Mitsubishi Electric Corporation
    Inventor: Shoichi KUGA
  • Publication number: 20170178860
    Abstract: A technique disclosed in the present specification relates to an ion implanter capable of preventing a semiconductor substrate from being damaged by an abnormal electric discharge through a simple method. The ion implanter of this technique includes an ion irradiation unit configured to irradiate a surface of a semiconductor substrate with ions. The ion implanter also includes at least one electrode (needle electrode, annular electrode) disposed in a position in the vicinity of at least one of back and side surfaces of an end of the semiconductor substrate. The position is dischargeable to and from the semiconductor substrate. The at least one electrode (needle electrode, annular electrode) is spaced apart from the semiconductor substrate.
    Type: Application
    Filed: July 11, 2016
    Publication date: June 22, 2017
    Applicant: Mitsubishi Electric Corporation
    Inventor: Shoichi KUGA
  • Patent number: 8778133
    Abstract: A method of peeling a protective tape, includes the steps of mounting a wafer on a stage, the wafer having the protective tape adhered thereto so that the protective tape overlaps only a portion of a notch of the wafer, attaching a peeling adhesive tape to the protective tape, projecting a lift pin from the stage so that the portion of the protective tape which overlaps the notch is raised by a top surface of the lift pin, and with the protective tape raised by the lift pin, pulling the peeling adhesive tape so as to peel the protective tape from the wafer. The top surface of the lift pin has a shape that allows the top surface to raise the portion of the protective tape which overlaps the notch.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: July 15, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Shoichi Kuga
  • Publication number: 20130098542
    Abstract: A method of peeling a protective tape, includes the steps of mounting a wafer on a stage, the wafer having the protective tape adhered thereto so that the protective tape overlaps only a portion of a notch of the wafer, attaching a peeling adhesive tape to the protective tape, projecting a lift pin from the stage so that the portion of the protective tape which overlaps the notch is raised by a top surface of the lift pin, and with the protective tape raised by the lift pin, pulling the peeling adhesive tape so as to peel the protective tape from the wafer. The top surface of the lift pin has a shape that allows the top surface to raise the portion of the protective tape which overlaps the notch.
    Type: Application
    Filed: December 14, 2012
    Publication date: April 25, 2013
    Inventor: Shoichi KUGA
  • Publication number: 20110220296
    Abstract: A method of peeling a protective tape, includes the steps of mounting a wafer on a stage, the wafer having the protective tape adhered thereto so that the protective tape overlaps only a portion of a notch of the wafer, attaching a peeling adhesive tape to the protective tape, projecting a lift pin from the stage so that the portion of the protective tape which overlaps the notch is raised by a top surface of the lift pin, and with the protective tape raised by the lift pin, pulling the peeling adhesive tape so as to peel the protective tape from the wafer. The top surface of the lift pin has a shape that allows the top surface to raise the portion of the protective tape which overlaps the notch.
    Type: Application
    Filed: December 28, 2010
    Publication date: September 15, 2011
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Shoichi KUGA