Patents by Inventor Shoichi Miyahara
Shoichi Miyahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11777447Abstract: An oscillation circuit according to the present invention includes a first oscillation circuit including a first diode having a first negative differential resistance and first composite inductor having a first inductor and a second inductor connected in series to the first diode in series. The oscillation circuit also includes a second diode that has a second negative differential resistance that is connected to the first inductor in parallel, and a third diode having a third negative differential resistance is connected to the first diode in series and is also connected to the first composite inductor in parallel. A burst pulse is output from a common connection point of the first inductor, the second inductor, and the second diode.Type: GrantFiled: October 4, 2022Date of Patent: October 3, 2023Assignee: FUJITSU LIMITEDInventors: Kenichi Kawaguchi, Shoichi Miyahara
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Publication number: 20230021543Abstract: An oscillation circuit includes a first oscillation circuit that includes: a first diode that has a first negative differential resistance; a first composite inductor in which a first inductor and a second inductor are connected in series, is connected to the first diode in series; a second diode that has a second negative differential resistance and is connected to the first inductor in parallel; and a third diode that has a third negative differential resistance, is connected to the first diode in series, and is connected to the first composite inductor in parallel, wherein a burst pulse is output from a common connection point of the first inductor, the second inductor, and the second diode.Type: ApplicationFiled: October 4, 2022Publication date: January 26, 2023Applicant: FUJITSU LIMITEDInventors: Kenichi Kawaguchi, Shoichi MIYAHARA
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Publication number: 20230023123Abstract: A reservoir includes a common input layer, first and second output layers that outputs a first and a second readout values based on an input, a first partial reservoir including the input layer and the first output layer, and a second partial reservoir having a size between the input layer and the second output layer larger than the size of the first partial reservoir, and the training processing including: first calculating a third output weight that reduces a difference between a first product sum value of a third readout value and a first output weight; and second calculating a fourth output weight that reduces a difference between a second product sum value of a fourth readout value and a second output weight and differential teaching data that is a difference between a third product sum value of the third readout value and the third output weight and the teaching data.Type: ApplicationFiled: October 3, 2022Publication date: January 26, 2023Applicant: FUJITSU LIMITEDInventor: Shoichi MIYAHARA
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Publication number: 20210081772Abstract: A reservoir designing method executed by a computer configured to control a neural network including a reservoir and an output layer, the reservoir including a plurality of nodes and having a coupling structure randomly determined between the plurality of nodes, the output layer having a weight set on each node of the plurality of nodes. In an example, the method includes: changing the coupling structure between the plurality of nodes included in the reservoir; computing an output for an input to the neural network; updating the weight of the output layer based on the output for each of the coupling structures changed by the changing; evaluating the output according to a predetermined criterion; and selecting a predetermined coupling structure from the coupling structures changed by the changing based on an evaluation result obtained by the evaluating.Type: ApplicationFiled: August 7, 2020Publication date: March 18, 2021Applicant: FUJITSU LIMITEDInventor: Shoichi MIYAHARA
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Patent number: 10679969Abstract: An electronic circuit device includes a first electronic component having a set of first terminals disposed at a first pitch on a first surface, and a second electronic component having a set of second terminals disposed at a second pitch on a second surface facing the first surface of the first electronic component. The second pitch of the second terminals is set larger than the first pitch of the first terminals. By doing so, each of the second terminals is connected to at least one of the first terminals if a positional misalignment occurs. As a result, the electronic circuit device has an increased tolerance for positional misalignment between the first electronic component and the second electronic component and reduces the occurrence of connection failure.Type: GrantFiled: February 22, 2018Date of Patent: June 9, 2020Assignee: FUJITSU LIMITEDInventor: Shoichi Miyahara
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Patent number: 10319667Abstract: An electronic device includes: a substrate that includes a first penetration hole; a first electrode that is located on a first surface of the substrate so as to cover the first penetration hole; and a first penetrating electrode that is located in the first penetration hole and is in contact with or away from the first electrode depending on temperature.Type: GrantFiled: July 5, 2017Date of Patent: June 11, 2019Assignee: FUJITSU LIMITEDInventors: Shoichi Miyahara, Aki Dote, Hideki Kitada
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Publication number: 20180247917Abstract: An electronic circuit device includes a first electronic component having a set of first terminals disposed at a first pitch on a first surface, and a second electronic component having a set of second terminals disposed at a second pitch on a second surface facing the first surface of the first electronic component. The second pitch of the second terminals is set larger than the first pitch of the first terminals. By doing so, each of the second terminals is connected to at least one of the first terminals if a positional misalignment occurs. As a result, the electronic circuit device has an increased tolerance for positional misalignment between the first electronic component and the second electronic component and reduces the occurrence of connection failure.Type: ApplicationFiled: February 22, 2018Publication date: August 30, 2018Applicant: FUJITSU LIMITEDInventor: Shoichi MIYAHARA
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Patent number: 9920428Abstract: A film deposition apparatus includes: a plasma generating section configured to generate plasma between a cathode target and an anode; a film deposition chamber in which a base material is placed; and a magnetic-field filter section configured to remove a particle from the plasma by a magnetic field and to transfer the plasma to the film deposition chamber. The magnetic-field filter section includes: a first housing area to which a first voltage is applied; and a second housing area, provided downstream of the first housing area in the moving direction of the plasma, to which a second voltage is applied.Type: GrantFiled: December 10, 2015Date of Patent: March 20, 2018Assignee: FUJITSU LIMITEDInventors: Norikazu Nakamura, Shoichi Miyahara, Hiroshi Chiba
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Publication number: 20180061740Abstract: An electronic device includes: a substrate that includes a first penetration hole; a first electrode that is located on a first surface of the substrate so as to cover the first penetration hole; and a first penetrating electrode that is located in the first penetration hole and is in contact with or away from the first electrode depending on temperature.Type: ApplicationFiled: July 5, 2017Publication date: March 1, 2018Applicant: FUJITSU LIMITEDInventors: Shoichi Miyahara, Aki Dote, Hideki Kitada
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Patent number: 9567674Abstract: A film deposition apparatus includes: a plasma generating section configured to generate plasma between a cathode target and an anode; a film deposition chamber in which a base material is placed; and a magnetic-field filter section configured to remove a particle from the plasma by a magnetic field and to transfer the plasma to the film deposition chamber. The magnetic-field filter section includes: a first housing area to which a first voltage is applied; and a second housing area, provided downstream of the first housing area in the moving direction of the plasma, to which a second voltage is applied.Type: GrantFiled: June 2, 2010Date of Patent: February 14, 2017Assignee: FUJITSU LIMITEDInventors: Norikazu Nakamura, Shoichi Miyahara, Hiroshi Chiba
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Publication number: 20160194757Abstract: A film deposition apparatus includes: a plasma generating section configured to generate plasma between a cathode target and an anode; a film deposition chamber in which a base material is placed; and a magnetic-field filter section configured to remove a particle from the plasma by a magnetic field and to transfer the plasma to the film deposition chamber. The magnetic-field filter section includes: a first housing area to which a first voltage is applied; and a second housing area, provided downstream of the first housing area in the moving direction of the plasma, to which a second voltage is applied.Type: ApplicationFiled: December 10, 2015Publication date: July 7, 2016Applicant: FUJITSU LIMITEDInventors: Norikazu Nakamura, Shoichi Miyahara, Hiroshi Chiba
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Publication number: 20100316814Abstract: A film deposition apparatus includes: a plasma generating section configured to generate plasma between a cathode target and an anode; a film deposition chamber in which a base material is placed; and a magnetic-field filter section configured to remove a particle from the plasma by a magnetic field and to transfer the plasma to the film deposition chamber. The magnetic-field filter section includes: a first housing area to which a first voltage is applied; and a second housing area, provided downstream of the first housing area in the moving direction of the plasma, to which a second voltage is applied.Type: ApplicationFiled: June 2, 2010Publication date: December 16, 2010Applicant: FUJITSU LIMITEDInventors: Norikazu Nakamura, Shoichi Miyahara, Hiroshi Chiba
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Publication number: 20100003422Abstract: A deposition apparatus includes a plasma generating unit that generates an arc discharge between a target and an anode to generate plasma; a deposition chamber in which a base is disposed; and a plasma transfer unit that transfers the plasma to the deposition chamber, wherein at least part of the plasma transfer unit is electrically separated from the plasma generating unit and the deposition chamber, and a negative voltage is applied to at least part of the plasma transfer unit.Type: ApplicationFiled: June 8, 2009Publication date: January 7, 2010Applicant: FUJITSU LIMITEDInventors: Norikazu NAKAMURA, Shoichi MIYAHARA, Yukiko OSHIKUBO, Hiroshi CHIBA
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Patent number: 6045975Abstract: The film forming, photosensitive, heat-resistant resin composition comprising a varnish of a polyimide precursor having no photosensitivity in itself, a polymerizable monomer or oligomer compatible with said varnish and capable of providing a high-heat-resistant polymer upon being polymerized, and a polymerization initiator for said monomer or oligomer. The resin composition is useful for the production of circuit substrates and semiconductor devices for high-density mounting including multi-chip modules or the like, such as printed circuits, printed boards, wiring boards and electronic components, since it can effectively avoid a reduction of the layer thickness during the film formation, and ensures a low cost production process. The pattern formation process using the such resin composition is also disclosed.Type: GrantFiled: May 21, 1993Date of Patent: April 4, 2000Assignee: Fujitsu LimitedInventors: Motoaki Tani, Eiji Horikoshi, Isao Watanabe, Shoichi Miyahara, Takashi Ito, Makoto Sasaki
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Patent number: 6013419Abstract: A method for forming a photosensitive, heat-resistant resin composition film including the step of coating a base material with a varnish made up of a polyimide precursor having no photosensitivity, a photopolymerizable monomer or oligomer capable of providing a high-heat-resistant polymer upon being polymerized, and a polymerization initiator for the monomer or oligomer. The coating is exposed to a light pattern to polymerize the monomer or oligomer in a pattern. The remaining coating is selectively removed from the non-patterned areas. The patterned coating is heat treated to cure the polyimide precursor, thereby forming the film.Type: GrantFiled: April 6, 1995Date of Patent: January 11, 2000Assignee: Fujitsu LimitedInventors: Motoaki Tani, Eiji Horikoshi, Isao Watanabe, Shoichi Miyahara, Takashi Ito, Makoto Sasaki
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Patent number: 5972807Abstract: A film forming, photosensitive, heat-resistant resin composition including a varnish of a polyimide precursor having no photosensitivity in itself, a polymeriziable monomer or oligomer compatible with the varnish and capable of providing a high-heat-resistant polymer upon being polymerized, and a polymerization initiator for the monomer or oligomer. The resin composition is useful for the production of circuit substrates and semiconductor devices for high-density mounting, since it can effectively avoid a reduction of the layer thickness during film formation, and ensures a low cost production process. The pattern formation process using such a resin composition is also disclosed. The polymeric composite having a particles-in-matrix microstructure and the production process thereof are also disclosed.Type: GrantFiled: December 23, 1996Date of Patent: October 26, 1999Assignee: Fujitsu LimitedInventors: Motaki Tani, Eiji Horikoshi, Isao Watanabe, Shoichi Miyahara, Takashi Ito, Makoto Sasaki
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Patent number: 5308929Abstract: A via hole structure for interlayer connection formed in an insulating film and a process for the formation of the same. Via holes are formed in an insulating film of a multilayer interconnected board or the like so as to have a shape such that when a metallic film for wiring is formed on the insulating film, the metal film can completely fill up the via holes. The via holes are formed by gradually increasing from the bottom toward the top of an insulating layer 8 the apertures of the via holes 7 formed in the insulating layer 8, comprised of a plurality of insulating resin film or photosensitive insulating resin film layers 2, 5, in a multilayer interconnected board comprising the insulating layer 8 laminated alternately with a wiring layer 13 comprised of an electric conductor.Type: GrantFiled: July 27, 1992Date of Patent: May 3, 1994Assignee: Fujitsu LimitedInventors: Motoaki Tani, Shoichi Miyahara, Makoto Sasaki, Eiji Horikoshi, Isao Kawamura