Abstract: Supplied with carrier and channel selection signals in a VOD receiver from a remote control data processor from a remote control switch, a switching control circuit produces demodulation and equalization control signals substantially concurrently with carrier switching started by the carrier selection signal. In response, a demodulator and a digital transversal equalizer are held in a held state. Immediately after completion of the carrier switching, the demodulator and the equalizer are turned back to an automatically controlled state to be operable with synchronism kept. While demodulation and equalization are held, a digital signal processor produces a receiver output video signal for standstill picture scenes. Immediately upon turn back of the demodulation and the equalization, the channel selection signal makes the output video signal represent moving picture scenes. The digital transversal equalizer may be an analog one connected to the demodulator.

Abstract: In a modulation system, a demodulator demodulates an intermediate frequency modulated signal and outputs an analog-baseband signal, and an analog-digital converter analog-digital converts this baseband signal. An adaptive matched filter inputs the output of the analog-digital converter and makes symmetrical the impulse response of the propagation path. A decision feedback equalizer inputs the output of the adaptive matched filter and eliminates the intersymbol interference. A reset circuit judges the fading type using tap coefficients within the decision feedback equalizer, and stops the operation of the adaptive matched filter in cases of minimum phase shift type fading. The adaptive matched filter is constructed so as to operate in an intermediate frequency band as well as in a baseband.

Abstract: In a cross polarization interference canceller for use in digital radio communications, a signal processing circuit monitors whether numbers of word sync signals and error pulses obtained in error correction decoding exceed specified values, and outputs reset signal RS1 when an abnormality is detected. A signal level detection circuit outputs reset signal RS2 when it is detected that a level of a different polarization side baseband signal from a demodulator is lower than specified. A logical sum RS3 of reset signals RS1 and RS2 is supplied to a cross polarization interference cancellation device, which may have a transversal filter. When the word is not synchronized or the number of error pulses generated in error correcting decoding exceeds the specified value, the self-polarization side can be protected from unnecessary interference and disturbance and the self-polarization side data can be protected from disturbance even though an abrupt abnormality occurs in different polarization signals.

Abstract: An automatic equalizer includes an adaptive matched filter connected in front of a decision feedback equalizer of a conventional design. The adaptive matched filter has an A/D converter for sampling and quantizing an analog baseband signal into a digital signal, which is applied to a transversal filter. The transversal filter is supplied with tap coefficients adaptively controlled by a control signal generator which makes automatic adjustments to symmetrize the impulse response of a transmission path depending on the status of fading. The automatic equalizer can sufficiently equalize the fading in the range .rho.>1 in which the reflected wave is stronger than the direct wave, which fading cannot be adequately equalized only by the conventional decision feedback equalizer.

Abstract: For use in combination with a demodulator (23) for demodulating a received signal susceptible to fading into a demodulated signal, an adaptive equalizer comprises a fading detecting circuit (51) for detecting the received signal to produce a detection signal representative of a magnitude of the fading. Into a processed signal and supplied with the detection signal, an equalizer multiplier (53) processes an equalized signal produced in an equalizer section (25, 26 and 27) which is for carrying out a predetermined equalization operation. In accordance with the processed signal, an automatic gain control circuit (52) modifies the demodulated signal into a modified signal on which the predetermined equalization operation is carried out.

Abstract: A decision feedback equalizer for equalizing a received analog baseband signal (1) has a gain control circuit (11) which compresses the amplitude of the baseband signal (1) to 1/K (K.gtoreq.1). The compressed signal is converted to a digital signal by an analog-to-digital converter (12). A decision feedback equalizer section (101) has a feedforward equalizer (201) to which the digital signal is applied, a feedback equalizer (202), and an adder (13) for adding the outputs of the feedforward and feedback equalizers. A postprocessor (15) discriminates the adder output (S1') which has been multiplied by K to thereby output a received data signal (d) and a discrimination error signal (e). An expansive decision circuit (104) expands the adder output by L times (L>1), discriminates the expanded signal, and delivers the result of discrimination to the feedback equalizer (202). A control signal generator (102) feeds tap coefficients to the feedforward and feedback equalizers.

Abstract: In a cross-polarization interference canceller employing a transversal filter, when a tap coefficient of the transversal filter is generated by averaging resultant values of correlation between a residual error component and a data polarity signal of a different polarized wave, a moving average derived by averaging with a sum of most recent given number of bits of correlation results, is employed. Even when offset is caused on the correlation results due to random characteristics of the received signal, the offset cannot be accumulated to allow derivation of the true tap coefficient since the sum of most recent given number of bits of correlation results is used.

Abstract: In a demodulating system for demodulating a modulated signal into decoded signals (S11'-12', S21'-22'), an error signal correcting circuit (55) is used in correcting discrimination error signals (Ep, Eq) supplied from a demodulator (52) in compliance with error location signals (Sp1-2, Sq1-2) supplied from an error-correcting decoder (54) and in producing corrected discrimination error signals (Ep', Eq') for supply to an adaptive equalizer (51) which is additionally supplied with polarity signals (Dp, Dq) from a delay circuit (53). The modulated signal is equalized in accordance with the corrected discrimination error signals and the polarity signals, demodulated into demodulated signals and the discrimination error signals, and error corrected and decoded into the decoded signals. The delay circuit delays P-channel and Q-channel polarity bits of the demodulated signal into the polarity signals.

Abstract: In a cross-polarization interference conceller for use in a digital radio communication system which transmits digital modulated signals over radio frequencies having planes of polarization orthogonal to each other, signals from the interfering polarized wave are sampled with a frequency equal to double the frequency of the affected polarized wave and, after latching the sampled signals with the frequency of the symbol rate, interference cancelling signals are generated by adding the products of their multiplication with control signals. Therefore, the digital multipliers and the digital adders for generating the interference cancelling signals can be operated at low speed.

Abstract: In a parallel-mode adaptive transversal equalizer, P- and Q-channel data streams from A/D converters (1, 5) are respectively passed through the tapped-delay lines of trasversal filters (2, 6), on the one hand, and are one-symbol delayed, on the other, by delay circuits (3, 7, 66, 67) to produce (N-1) successively delayed P- and Q-channel data streams, which are respectively passed through the tapped delay lines of transversal filters (4; 63, 8; 64). In each trasversal filter, symbols appearing at successive taps of the tapped-delay line are sampled and held for a duration of N symbols to produce first and second groups of stored symbols, the stored symbols of the first group being multiplied by first tap weights and summed, producing N first equalized outputs for each channel. The stored symbols of the second are multiplied by second tap weights and summed, producing N second equalized outputs for each channel.

Abstract: In an adaptive equalizer system for equalizing, in response to a plurality of controllable tap gains, a received signal carrying a transmission data sequence digitized by a reference clock signal, a correlation detecting circuit (63') comprises a divider (111) for frequency dividing a reproduced clock signal representative of a reproduction of the reference clock signal to produce a divided clock signal. A serial-parallel converter (120) is for converting a reproduced data sequence representative of a reproduction of the transmission data sequence and a digital error signal relative to the reproduced data sequence into a plurality of converted data sequences and a plurality of converted error signals in synchronism the divided clock signal. As Exclusive logic circuit (70) is for carrying out an exclusive logic operation on the converted error signals and the converted data sequences to produce a plurality of correlation signals which are collectively used in controlling the controllable tap gains.

Abstract: In a demodulator for demodulating a multilevel quadrature amplitude modulated signal specified by a plurality of output signal points arranged on an approximately octangular specific region into an in-phase baseband signal and a quadrature baseband signal and for converting the in-phase and the quadrature baseband signals into a demodulator output signal and an error signal, a validity decision circuit (40) is supplied with the in-phase and the quadrature baseband signals to decide that the error signal is valid when at least one reception signal point is outwardly of the approximately octangular specific region.

Abstract: In order to rapidly bring a 8-phase phase shift keying demodulator into resynchronization upon the demodulator going out of synchronism, a plurality of error signals produced within the demodulator is used to determine whether a signal point of an incoming 8-phase phase modulated signal is usable for controlling a transversal filter. An asynchronism signal, which indicates whether the demodulator is synchronized, is derived from the demodulator and being applied to a tap gain control signal generator coupled to the transversal filter. The tap gain control signal generator is controlled when the asynchronism signal indicates asynchronism of the demodulator.

Abstract: In order to remove at least one of amplitude and delay distortions which tend to occur during signal transmission, the invention features circuitry wherein a received IF digital signal is fed through an equalizer circuit to a demodulator and wherein the demodulator outputs a series of data and error signals to a control signal generator. The control signal generator produces in-phase and quadrature control signals which are appropriately added and subtracted and subsequently averaged in an adder and subtracter circuit before being applied to a series of equalizers in the equalizer circuit.

Abstract: In an equalizer for equalizing, by the use of zero forcing algorithm, an input signal obtained by modulating a carrier wave of a carrier frequency at a modulation rate, a specific one of complex control signals is modified into a modified complex signal and supplied to a specific one of gain control circuits of a transversal filter corresponding to a specific one of additional taps except a central tap. The modified complex signal is produced by rotating a phase of the specific complex control signal by a step equal to an integral multiple of .pi./2. Specifically, at least one of real and imaginary parts of the modified complex signal is inverted relative to those of the specific complex control signal. The real and the imaginary parts of the modified control signal are delivered to in-phase and quadrature portions of the specific gain control circuit in consideration of the step.

Abstract: The present invention features an automatic adaptive equalizer which detects asynchronism in a demodulator coupled to the equalizer and intermittently generates a reset signal. This signal intermittently renders a transversal filter of the adpative equalizer operative during a period in which the filter is normally rendered inoperative by a control loop of the adaptive equalizer.