Abstract: A method for designing routes for multilevel interconnections in a semiconductor device having at least a field effect transistor having a gate electrode, where the route extends between a diffusion region and the gate electrode. Each interconnection connected to the gate electrode is given an area which does not exceed a predetermined antenna effect reference value by inserting a buffer, such as a logic gate, into the interconnection on the same level as the interconnection.

Abstract: In a shift and shift-out detecting circuit, a plurality of partial shift circuits respectively have bit shift quantities which are different from each other, and are connected in series. Each of the plurality of partial shift circuits receives a shift result as a previous shift result from the partial shift circuit of a previous stage and a corresponding shift instruction, shifts the previous shift result by the corresponding bit shift quantity in response to the shift instruction to produce a current shift result, and outputs the current shift result to the partial shift circuit of a subsequent stage. A plurality of shift-out detecting circuits are respectively provided for the plurality of partial shift circuits. Each of the plurality of shift-out detecting circuits detects a shift-out of “1” bit from the current shift result and the corresponding shift instruction and generates a partial sticky signal when the shift-out is detected.

Abstract: A nozzle rod is formed by fixing a thick diamond chip to a tip of a nozzle pipe made of a super hard metal, the other end of the nozzle pipe is thinned and the nozzle rod is joined with a shank by way of this end, a tip of the nozzle rod and vicinities thereof are so shaped as to have a predetermined sectional shape, a center hole is formed in the diamond chip by wire electro spark machining and expanded for forming a nozzle slot having a nozzle opening consisting of a center slit and “U-shaped” slits which are disposed symmetrically on both sides of a longitudinal direction of the center slit, thereby composing an electronic part adsorbing nozzle. This construction enables it to provide an electronic part adsorbing nozzle which is economical and excellent in durability.

Abstract: The present invention provides a layout design method for routine of a route comprising multilevel interconnections in a semiconductor device having at least a field effect transistor having a gate electrode, and the route extending between a diffusion region and the gate electrode, wherein each interconnection being connected to the gate electrode and being not connected to the diffusion region, when the each interconnection is patterned, has an area which does not exceed a predetermined reference value.

Abstract: A nozzle rod (1) is formed by fixing a thick diamond chip (2) to a tip of a nozzle pipe (4) made of a super hard metal, the other end of the nozzle pipe (4) is thinned and the nozzle rod (1) is joined with a shank (5) by way of this end, a tip of the nozzle rod (1) and vicinities thereof are so shaped as to have a predetermined sectional shape, a center hole is formed in the diamond chip (2) by wire electrospark machining and expanded for forming a nozzle slot (10) having a nozzle opening (11) consisting of a center slit (12) and "U-shaped" slits (13, 14) which are disposed symmetrically on both sides of a longitudinal direction of the center slit (12), thereby composing an electronic part adsorbing nozzle (7). This construction enables it to provide an electronic part adsorbing nozzle (7) which is economical and excellent in durability.