Abstract: A method for performing multi-wire signaling decoding is provided. A raw symbol spread over a plurality of n wires is received via a plurality of differential receivers. The raw symbol is converted into a sequential number from a set of sequential numbers. Each sequential number is converted to a transition number. A plurality of transition numbers is converted into a sequence of data bits. A clock signal is then extracted from the reception of raw symbols.

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two or more devices within an electronic apparatus. Embodiments disclosed herein relate to scanning for slave identifiers (SIDs) on a CCIe bus. A disclosed method includes transmitting a first inquiry on a control data bus, where the first inquiry includes a first configuration of bits, determining presence of a slave device that has a slave identifier that includes a second configuration of bits that matches the first configuration of bits, and repetitively transmitting additional inquiries on the control data bus with different configurations of bits until all bits of the slave identifier are determined. The slave device may assert a response to each inquiry that includes a configuration of bits that matches a corresponding configuration of bits in the slave identifier.

Abstract: System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. CCI extension (CCIe) devices are described. CCIe devices may be configured as a bus master or as a slave. In one method, a CCIe transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A CCIe receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols.

Abstract: System, methods and apparatus are described that support multimode operation of a data communication interface. A method includes initializing a scrambler with a first pseudo-random binary sequence (PRBS) seed word after receiving a first sync word, the first sync word preceding a first packet, using the scrambler and the first PRBS seed word to scramble a first copy of a packet header that succeeds the first sync word in the first packet, initializing the scrambler with a second PRBS seed word after scrambling the first copy of the packet header, the second sync word succeeding the first copy of the packet header in the first packet, using the scrambler and the second PRBS seed word to scramble a second copy of the packet header that succeeds the second sync word in the first packet.

Abstract: System, methods and apparatus offer improved coexistence of devices on a serial bus. A bus master coupled to a serial bus transmits a start condition on the serial bus, and a first series of pulses on a clock line of the serial bus, the pulses having a duration that is less than a maximum duration for spikes to be filtered in accordance with the I2C protocol. The bus master transmits a second series of pulses on the clock line, the pulses having a duration that is greater than or equal to a minimum duration for clock pulses defined by the I2C protocol, and uses the second series of pulses to transmit a data frame on the serial bus in accordance with a different protocol. A stop condition is transmitted on the serial bus in accordance with the I2C protocol after transmission of the data frame is completed.

Abstract: A method and an apparatus are provided. The apparatus may includes a clock recovery circuit having a plurality of input latches configured to assume a first state when a first pulse is received in one or more of a plurality of input signals, combinational logic configured to provide a second pulse response to the first pulse, a delay circuit configured to produce a third pulse on a receive clock that is delayed with respect to the second pulse, a plurality of output flip-flops configured to capture the first state when triggered by the third pulse. The first state may identify which of the plurality of input signals received input pulses.

Abstract: A self-identification system is provided for slave devices that share a bus with a plurality of other identical slave devices. Each slave device may include two or more additional interfaces (e.g., single line), distinct from the shared bus, and coupled to at least one adjacent slave device. A protocol known to the master and slave devices is used to allow each slave device to identify itself without the need to explicitly transmit a unique identifier between the master device and the slave devices. The plurality of slave devices are daisy chained via the first and second interfaces, which are selectively driven and/or weakly pulled up or down in response to one or more broadcasts from the master device. Based on the state of their first and second interface, a slave device may respond to a broadcast and thus implicitly provides an identifier to the master device.

Abstract: System, methods and apparatus are described that include a serial bus, including a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. The bus has a first line and a second line, a first set of devices coupled to the bus and a second set of devices coupled to the bus. A method of operating the bus includes configuring the first set of devices to use the first line for data transmissions and use the second line for a first clock signal in a first mode of operation, and configuring the second set of devices to use both the first line and the second line for data transmissions while embedding a second clock signal within symbol transitions of the data transmissions in a second mode of operation.

Abstract: System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. CCI extension (CCIe) devices are described. CCIe devices may be configured as a bus master or as a slave. In one method, a CCIe transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A CCIe receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols.

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. A first transition may be detected in a signal carried on a data lane of a data communications link or carried on a timing lane of the data communications link and an edge may be generated on a receiver clock signal based on the first transition. Data may be captured from the data lane using the receiver clock signal. The timing lane may carry a clock signal, a strobe signal or another signal providing timing information. The strobe signal may transition between signaling states when no state transition occurs on any of a plurality of data lanes at a boundary between consecutive data periods.

Abstract: A method for enabling 8-bit data word access over a protocol limited to 16-bit data word access is provided. Data may be encapsulated within the lowest 19 bits of a 20-bit number. If it is ascertained that an 8-bit data word is to be used in a system supporting only 16-bit data word access, a byte-enable indicator may be provided within a most significant bit of the 20-bit number while also allocating an 8-bit data region for transfer of the 8-bit data word. The 20-bit number may then be transcoded into a 12-digit ternary number, wherein a residual numerical region is defined as a number space by which a first numerical region defined for the 12-digit ternary number exceeds a second numerical region defined by the lowest 19 bits of the 20-bit number.

Abstract: To accommodate multiple masters over bus architectures supporting a single master device, a mechanism is provided for an inactive master device to trigger an IRQ signal over a shared, single line IRQ bus. A current master then polls the other inactive master devices over a shared data bus to ascertain which inactive master device is asserting the IRQ signal. Upon identifying the asserting inactive master device, the current master device grants control of the data bus to the new master device, thereby making the inactive master the new active master device.

Abstract: A method and an apparatus are provided. The apparatus may includes a clock recovery circuit having a comparator that provides a comparison signal indicating whether an input signal matches a level-latched instance of the input signal, a first set-reset latch that provides a filtered version of the comparison signal, where the first set-reset latch is set by a first-occurring active transition of the comparison signal and is unaffected by further transitions of the comparison signal that occur during a predefined period of time, delay circuitry that receives the filtered version of the comparison signal and outputs a first pulse on a first clock signal, and a second set-reset latch configured to provide a second pulse on an output clock signal when the first pulse is present on the first clock signal and the comparison signal indicates that the level-latched instance of the input signal does not match the input signal.

Abstract: A method and an apparatus are provided. The apparatus may includes a clock recovery circuit having a plurality of input latches configured to assume a first state when a first pulse is received in one or more of a plurality of input signals, combinational logic configured to provide a second pulse response to the first pulse, a delay circuit configured to produce a third pulse on a receive clock that is delayed with respect to the second pulse, a plurality of output flip-flops configured to capture the first state when triggered by the third pulse. The first state may identify which of the plurality of input signals received input pulses.

Abstract: System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A sequence of data bits is converted into M transition numbers, which are then converted into a sequence of symbols. The sequence of symbols is transmitted received over N wires. A clock signal may be effectively embedded in the transmission of the sequence of symbols. Each of the sequence of symbols may be selected based on a corresponding one of the M transition numbers and a value of a preceding one of the sequence of symbols.

Abstract: A method, an apparatus, and a computer program product are described. The apparatus generates a receive clock signal for receiving data from a multi-wire open-drain link by determining a transition in a signal received from the multi-wire open-drain link, generating a clock pulse responsive to the transition, delaying the clock pulse by a preconfigured first interval if the transition is in a first direction, and delaying the clock by a preconfigured second interval if the transition is in a second direction. The preconfigured first and/or second intervals are configured based on a rise time and/or a fall time associated with the communication interface and may be calibrated by measuring respective delays associated with clock pulses generated for first and second calibration transitions.

Abstract: Systems, methods and apparatus are described for use in a communications link having a number of connectors. A method for communication using differential signaling with symbol transition clocking signaling communicates symbols over a communications link without transmitting a clock signal in a dedicated lane of the communications link. At a receiver, clock information may be extracted without using a phase-locked loop. The method includes converting data bits into a plurality of transition numbers, converting the plurality of transition numbers into a sequence of symbols, and transmitting the sequence of symbols over a plurality of signal wires. A clock signal may be embedded in transitions between consecutive symbols in the sequence of symbols. Each consecutive pair of transition numbers in the plurality of transition numbers may include two transition numbers that are different from one another. The sequence of symbols may be transmitted as a plurality of differential signals.

Abstract: To accommodate multiple masters over bus architectures supporting a single master device, a mechanism is provided for an inactive master device to assert an in-band IRQ. A current master then polls the other inactive master devices over a shared data bus to ascertain which inactive master device is asserting the IRQ. Upon identifying the asserting inactive master device, the current master device grants control of the data bus to the new master device, thereby making the inactive master the new active master device.

Abstract: A first set of devices is coupled to a first bus, a second bus, and configured to communicate over the first bus according to a first communication protocol. A second set of devices is also coupled to the first bus and configured to communicate over the first bus according to both the first communication protocol and a second communication protocol. In a first mode, the first set of devices and second set of devices may concurrently communicate over the first bus using the first communication protocol. In a second mode, the second set of devices communicate using the second communication protocol over the bus, and the first set of devices to stop operating on the first bus. An enable command is sent by at least one of the second set of devices over a second bus to cause the first set of devices to resume activity over the first bus.

Abstract: A method, an apparatus, and a computer program product are described. The apparatus generates a receive clock signal for receiving data from a multi-wire open-drain link by determining a transition in a signal received from the multi-wire open-drain link, generating a clock pulse responsive to the transition, delaying the clock pulse by a preconfigured first interval if the transition is in a first direction, and delaying the clock by a preconfigured second interval if the transition is in a second direction. The preconfigured first and/or second intervals are configured based on a rise time and/or a fall time associated with the communication interface and may be calibrated by measuring respective delays associated with clock pulses generated for first and second calibration transitions.