Abstract: Provided is a sensor integrated circuit capable of reducing a signal transmission time from a sensor circuit to a signal processing time without impairing the accuracy of a final value. The sensor circuit 13 has an output resistance Rs, and includes an output 13a connected to a signal line 19 and a pixel 21 for an image sensor. A signal processing circuit 15 is connected to the output of the sensor circuit 13 via the signal line 19. The signal processing circuit 15a includes an input 16a having a first input capacitance value, and processes a signal received via the signal line 19 from the sensor circuit 13. A charging circuit 17 includes an output 17a and an input 17b connected to the signal line 19. The output 17a has an output resistance R2 smaller than the output resistance Rs, and the input 17b has an input capacitance value smaller than the first input capacitance value.

Abstract: A cyclic A/D converter 21 provides an amplification type noise cancellation process and cyclic A/D conversion in which a plurality of capacitors and an operational amplifier are shared without complicated processing. In the cyclic A/D converter 21, a gain stage 23 uses first to third capacitors 33, 35 and 37 and an operational amplifier circuit 39 to perform the process for noise cancellation and amplification to generate a difference signal between first and second signal levels. In the process for noise cancellation, the difference between the first signal level VR and the second signal level VS is generated. The amplification of this difference is carried out in conjunction with the process for noise cancellation. The gain stage 23 uses the first to third capacitors 33, 35 and 37 and the operational amplifier circuit 39 to perform the process for cyclic A/D conversion of the difference signal. A sub A/D converter circuit 25 receives a signal VOP from an output (e.g.

Abstract: An image sensor controls the gain of a pixel signal on a pixel-by-pixel basis and extends a dynamic range while maintaining a S/N ratio at a favorable level. A column unit in an image sensor is independently detects a level of each pixel signal and independently sets a gain for level of the signal. A photoelectric converting region unit has pixels arranged two-dimensionally with a vertical signal line for each pixel column to output each pixel signal. The column unit is on an output side of the vertical signal line. The column unit for each pixel column has a pixel signal level detecting circuit, a programmable gain control, a sample and hold (S/H) circuit. Gain correction is performed according to a result of a detected level of the pixel signal.

Abstract: A semiconductor element includes: a p-type semiconductor region; an n-type light-receiving surface buried region buried in the semiconductor region; an n-type charge accumulation region buried in the semiconductor region, continuously to the light-receiving surface buried region, establishing a deeper potential well depth than the light-receiving surface buried region; a charge read-out region configured to read out the charges accumulated in the charge accumulation region; an exhaust-drain region buried in the semiconductor region, configured to extract the charges from the light-receiving surface buried region; a first potential controller configured to extract the charges from the light-receiving surface buried region to the exhaust-drain region; and a second potential controller configured to transfer the charges from the charge accumulation region to the charge read-out region.

Abstract: A cyclic A/D converter which can reduce the number of reference voltages for D/A conversion is provided. The cyclic A/D converter (11) comprises a gain stage (15), an A/D converter circuit (17), a logic circuit (19), and a D/A converter circuit (21). In an operational action of the gain stage (15), an operational value (VOP) is generated by the use of an operational amplifier circuit (23) and capacitors (25, 27, 29). The gain stage (15) operates as receiving three kinds of voltage signal from the D/A converter circuit (21) by the switching of two kinds of voltage signal (VDA1, VDA2) to be applied to the capacitors (25, 27) in a switching circuit (31).

Abstract: At least one cell implementing a sensor array embraces a photoelectric-conversion accumulation element configured to generate and accumulate signal charges, a potential detection circuit configured to detect the signal charges generated by the photoelectric-conversion accumulation element as a potential change, and an amplification circuit configured to amplify the potential change and to transmit to an output-signal line. The photoelectric-conversion accumulation element and the potential detection circuit are connected in series between a first potential terminal and a second potential terminal, and the potential detection circuit has an insulated-gate transistor, which detects the potential change in a weak inversion state, in a period when an optical-communication signal is received.

Abstract: A magnetic array sensor circuit to process an output from a magnetic sensor array including a plurality of magnetic sensor elements arranged in an array. The circuit includes a regulating circuit to reduce an offset variation of the output from the magnetic sensor elements arranged in the array.

Abstract: The present invention provides a high-speed charge-transfer photodiode encompassing a first conductivity type semiconductor layer (20) serving as a charge-generation region; and a second conductivity type surface-buried region (21a) serving as a charge-transfer region of charges generated by the charge-generation region, wherein a specified direction in the surface-buried region (21a) provided along a plane parallel to a surface of the semiconductor layer (20) is assigned as a charge-transfer direction of the charges, and at least one of a variation of widths of the surface-buried region (21a) measured in an orthogonal direction to the charge-transfer direction and a variation of impurity concentration distributions of the surface-buried region (21a), which are measured along the charge-transfer direction, is determined such that an electric field distribution in the charge-transfer direction is constant.

Abstract: A distance image sensor capable of enlarging the distance measurement range without reducing the distance resolution is provided. A radiation source 13 provides first to fifth pulse trains PT1 to PT5 which are irradiated to the object as radiation pulses in the first to fifth frames arranged in order on a time axis. In each of the frames, imaging times TPU1 to TPU5 are prescribed at points of predetermined time ?TPD from the start point of each frame, also the pulses PT1 to PT5 are shifted respectively by shift amounts different from each other from the start point of the first to fifth frames. A pixel array 23 generates element image signals SE1 to SE5 each of which has distance information of an object in distance ranges different from each other using imaging windows A and B in each of five frames. A processing unit 17 generates an image signal SIMAGE by combining the element image signals.

Abstract: A rotation detecting apparatus capable of increasing the angle detecting precision without being affected by an offset signal resulting from a stress in a silicon chip. The rotation detecting apparatus includes a magnetic sensor array and a magnet rotatable in face-to-face relation with the magnetic sensor array. The magnetic sensor array includes a plurality of groups of sensor elements, each group including four sensor elements. The four sensor elements of each combined sensor element group are so arranged as to be oriented vertically and horizontally in four directions and connected parallel to each other.

Abstract: Charge generated in a photodiode is properly split for difference processing. An imaging element is constituted by a semiconductor such that a charge accumulation portion is connected to a light receiving portion using a buried photodiode and charge is split from the charge accumulation portion by a plurality of gates and is accumulated. An imaging device includes a control device performing control so as to accumulate charge that is generated by a photoelectric conversion at an exposure cycle synchronous with the light emission of a light source. The exposure cycle includes a first period for receiving reflection light from a subject illuminated by light from the light source and a second period for receiving light from the subject illuminated by an environmental light not including the light from the light source.

Abstract: A part of a semiconductor layer directly under a light-receiving gate electrode functions as a charge generation region, and electrons generated in the charge generation region are injected into a part of a surface buried region directly above the charge generation region. The surface buried region directly under a first transfer gate electrode functions as a first transfer channel, and the surface buried region directly under a second transfer gate electrode functions as a second transfer channel. Signal charges are alternately transferred to an n-type first floating drain region and a second floating drain region through the first and second floating transfer channels.

Abstract: A telescopic differential operational amplifier circuit for use in a pipelined A/D converter is provided with two auxiliary differential amplifiers connected to two cascode circuits, each including cascode-connected first to fourth transistors. During the sampling phase, first and second switches are turned on to apply a predetermined bias voltage to the gates of first and fourth transistors, and the input terminal of the differential operational amplifier circuit is set to a common mode voltage. During the hold phase, the first and second switches are turned off so that a voltage of each of the gates of the first and fourth transistors change to follow an input signal inputted via the input terminal with coupling capacitors operating as a level shifter of the input signal. Then the differential operational amplifier circuit performs push-pull operation operative only in a transconductance drive region, and is prevented from operating in a slewing region.

Abstract: A charge corresponding to an analog signal Vi is accumulated in first and second capacitors 25, 27, respectively. A digital signal VDIGN having a digital value (D1, D0, for example) corresponding to the analog signal Vi is generated. By connecting the second capacitor 27 between an output 21c and an inversion input 21a of an operational amplifier circuit 21 and supplying a first capacitor end 25a with an analog signal VD/A corresponding to the digital signal VDIGN, a first conversion value VOUT1 is generated in the output 21c of the operational amplifier circuit 21. By connecting the first and third capacitors 25, 33 between the output 21c and inversion input 21a of the operational amplifier circuit 21 and supplying a second capacitor end 27a with the analog signal VD/A, a second conversion value VOUT2 is generated in the output 21c of the operational amplifier circuit 21.

Abstract: The present invention relates to a CMOS image sensor having a wide dynamic range, which permits favorable imaging even in cases where a bright portion and a dark portion exist simultaneously. The dynamic range can be widened by preventing the saturation of optical charge at a high illuminance by removing low illuminance signals due to long-time accumulation, intermediate illuminance signals due to short-time accumulation, and high illuminance signals due to ultra-short time accumulation from pixel portions of the image sensor. Further, adaptive control of the dynamic range can also be performed by dynamically changing the wide dynamic range imaging conditions that comprise a combination of different accumulation times of each of a plurality of short time accumulation signals.

Abstract: A conversion operation B is performed with respect to a sample value R in an A/D conversion stage 101 to generate a conversion result D3, and a sampling operation A is performed with respect to this conversion result D3 in an A/D conversion stage 103. The conversion operation B is performed with respect to a sample value in an A/D conversion stage 105 to generate a conversion result D4, and the sampling operation A is performed with respect to the conversion result D4 in an A/D conversion stage 107. The conversion operation B is performed with respect to a sample value in an A/D conversion stage 107 to generate a conversion result D5, and the sampling operation A is performed with respect to this conversion result D5 in an A/D conversion stage 101. The conversion operation B is performed with respect to a sample value in the A/D conversion stage 103 to generate a conversion result D6, and the sampling operation A is performed with respect to the conversion result D6 in the A/D conversion stage 105.

Abstract: An n-type region as a charge storage region of a photodiode is buried in a substrate. The interface between silicon and a silicon oxide film is covered with a high concentration p-layer and a lower concentration p-layer is formed only in the portion immediately below a floating electrode for signal extraction. Electrons generated by light are stored in the charge storage region, thereby changing the potential of the portion of the p-layer at the surface of the semiconductor region. The change is transmitted through a thin insulating film to the floating electrode by capacitive coupling and read out by a buffer transistor. Initialization of charges is executed by adding a positive high voltage to the gate electrode of a first transfer transistor such that the electrons stored in the charge storage region are transferred to the n+ region and generation of reset noise is protected.

Abstract: A pre-amplifier (column region unit) of a solid-state imaging device including a pixel-signal controller. The pixel-signal controller, for each vertical signal line, detects the level of each pixel signal independently by a pixel-signal detector on the output side of a pixel-signal amplifier, and sets a gain independently to the pixel-signal amplifier according to the level of the signal. At a subsequent stage of the solid-state imaging device, an analog-to-digital (A/D) converter and a signal extending unit are provided. The A/D converter digitizes a pixel signal, and the digitized pixel signal is corrected by a gain set to the pixel-signal amplifier with reference to a classification signal from the pixel-signal detector, so that the dynamic range of signals of one screen is extended.

Abstract: A cyclic A/D converter 21 provides an amplification type noise cancellation process and cyclic A/D conversion in which a plurality of capacitors and an operational amplifier are shared without complicated processing. In the cyclic A/D converter 21, a gain stage 23 uses first to third capacitors 33, 35 and 37 and an operational amplifier circuit 39 to perform the process for noise cancellation and amplification to generate a difference signal between first and second signal levels. In the process for noise cancellation, the difference between the first signal level VR and the second signal level VS is generated. The amplification of this difference is carried out in conjunction with the process for noise cancellation. The gain stage 23 uses the first to third capacitors 33, 35 and 37 and the operational amplifier circuit 39 to perform the process for cyclic A/D conversion of the difference signal. A sub A/D converter circuit 25 receives a signal VOP from an output (e.g.

Abstract: An n-type region as a charge storage region of a photodiode is buried in a substrate. The interface between silicon and a silicon oxide film is covered with a high concentration p-layer and a lower concentration p-layer is formed only in the portion immediately below a floating electrode for signal extraction. Electrons generated by light are stored in the charge storage region, thereby changing the potential of the portion of the p-layer at the surface of the semiconductor region. The change is transmitted through a thin insulating film to the floating electrode by capacitive coupling and read out by a buffer transistor. Initialization of charges is executed by adding a positive high voltage to the gate electrode of a first transfer transistor such that the electrons stored in the charge storage region are transferred to the n+ region and generation of reset noise is protected.