Patents by Inventor Shoji Takei
Shoji Takei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240170436Abstract: A semiconductor device includes a semiconductor layer having a first surface, an insulating layer formed at the first surface of the semiconductor layer, a Cu conductive layer formed on the insulating layer, the Cu conductive layer made of a metal mainly containing Cu, a second insulating layer formed on the insulating layer, the second insulating layer covering the Cu conductive layer, a Cu pillar extending in a thickness direction in the second insulating layer, the Cu pillar made of a metal mainly containing Cu and electrically connected to the Cu conductive layer, and an intermediate layer formed between the Cu conductive layer and the Cu pillar, the intermediate layer made of a material having a linear expansion coefficient smaller than a linear expansion coefficient of the Cu conductive layer and smaller than a linear expansion coefficient of the Cu pillar.Type: ApplicationFiled: January 26, 2024Publication date: May 23, 2024Applicant: ROHM CO., LTD.Inventors: Shoji TAKEI, Yuji KOGA
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Patent number: 11961816Abstract: A semiconductor device includes a semiconductor layer having a first surface, an insulating layer formed at the first surface of the semiconductor layer, a Cu conductive layer formed on the insulating layer, the Cu conductive layer made of a metal mainly containing Cu, a second insulating layer formed on the insulating layer, the second insulating layer covering the Cu conductive layer, a Cu pillar extending in a thickness direction in the second insulating layer, the Cu pillar made of a metal mainly containing Cu and electrically connected to the Cu conductive layer, and an intermediate layer formed between the Cu conductive layer and the Cu pillar, the intermediate layer made of a material having a linear expansion coefficient smaller than a linear expansion coefficient of the Cu conductive layer and smaller than a linear expansion coefficient of the Cu pillar.Type: GrantFiled: July 8, 2022Date of Patent: April 16, 2024Assignee: ROHM CO., LTD.Inventors: Shoji Takei, Yuji Koga
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Publication number: 20240071908Abstract: A semiconductor device includes an interlayer insulating film, and a wiring of an uppermost layer arranged on the interlayer insulating film, wherein the wiring includes a seed layer arranged on the interlayer insulating film and a wiring body portion arranged on the seed layer, wherein a constituent material of the wiring body portion is copper or a copper alloy, and wherein a trench is formed in an upper surface of the interlayer insulating film along an outer edge of the interlayer insulating film in a plan view.Type: ApplicationFiled: August 23, 2023Publication date: February 29, 2024Applicant: ROHM CO., LTD.Inventors: Shoji TAKEI, Akinori NII
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Patent number: 11916034Abstract: A semiconductor device includes a semiconductor layer having a first surface, an insulating layer formed at the first surface of the semiconductor layer, a Cu conductive layer formed on the insulating layer, the Cu conductive layer made of a metal mainly containing Cu, a second insulating layer formed on the insulating layer, the second insulating layer covering the Cu conductive layer, a Cu pillar extending in a thickness direction in the second insulating layer, the Cu pillar made of a metal mainly containing Cu and electrically connected to the Cu conductive layer, and an intermediate layer formed between the Cu conductive layer and the Cu pillar, the intermediate layer made of a material having a linear expansion coefficient smaller than a linear expansion coefficient of the Cu conductive layer and smaller than a linear expansion coefficient of the Cu pillar.Type: GrantFiled: July 8, 2022Date of Patent: February 27, 2024Assignee: ROHM CO., LTD.Inventors: Shoji Takei, Yuji Koga
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Publication number: 20220399292Abstract: A semiconductor device includes: a semiconductor chip having an element forming surface; an insulating layer formed on the element forming surface; a pad wiring layer including a first conductive layer formed on the insulating layer and containing a first conductive material and a second conductive layer formed on the first conductive layer and containing a second conductive material different from the first conductive material, wherein the second conductive layer includes an eaves portion protruding outward with respect to an end surface of the first conductive layer; a bonding member bonded to the pad wiring layer and supplying electric power to an element of the element forming surface; and a coating insulating film selectively formed on the insulating layer below the eaves portion, exposing an upper surface of the insulating layer to a peripheral region of the pad wiring layer, and covering the end surface of the first conductive layer.Type: ApplicationFiled: May 19, 2022Publication date: December 15, 2022Applicant: ROHM CO., LTD.Inventor: Shoji TAKEI
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Publication number: 20220344299Abstract: A semiconductor device includes a semiconductor layer having a first surface, an insulating layer formed at the first surface of the semiconductor layer, a Cu conductive layer formed on the insulating layer, the Cu conductive layer made of a metal mainly containing Cu, a second insulating layer formed on the insulating layer, the second insulating layer covering the Cu conductive layer, a Cu pillar extending in a thickness direction in the second insulating layer, the Cu pillar made of a metal mainly containing Cu and electrically connected to the Cu conductive layer, and an intermediate layer formed between the Cu conductive layer and the Cu pillar, the intermediate layer made of a material having a linear expansion coefficient smaller than a linear expansion coefficient of the Cu conductive layer and smaller than a linear expansion coefficient of the Cu pillar.Type: ApplicationFiled: July 8, 2022Publication date: October 27, 2022Applicant: ROHM CO., LTD.Inventors: Shoji TAKEI, Yuji KOGA
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Publication number: 20220284726Abstract: An optical module includes: a first lens having a first principal surface and a second principal surface; and a second lens having a third principal surface and a fourth principal surface, the first principal surface is configured by a flat surface, and on the second principal surface, a concave lens array having a plurality of concave lenses is formed, and on each of the third principal surface and the fourth principal surface, a convex lens array having a plurality of convex lenses is formed, and the second principal surface and the third principal surface are arranged in such a way as to face each other.Type: ApplicationFiled: July 16, 2020Publication date: September 8, 2022Applicant: SONY GROUP CORPORATIONInventor: Shoji TAKEI
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Patent number: 11417623Abstract: A semiconductor device includes a semiconductor layer having a first surface, an insulating layer formed at the first surface of the semiconductor layer, a Cu conductive layer formed on the insulating layer, the Cu conductive layer made of a metal mainly containing Cu, a second insulating layer formed on the insulating layer, the second insulating layer covering the Cu conductive layer, a Cu pillar extending in a thickness direction in the second insulating layer, the Cu pillar made of a metal mainly containing Cu and electrically connected to the Cu conductive layer, and an intermediate layer formed between the Cu conductive layer and the Cu pillar, the intermediate layer made of a material having a linear expansion coefficient smaller than a linear expansion coefficient of the Cu conductive layer and smaller than a linear expansion coefficient of the Cu pillar.Type: GrantFiled: March 27, 2020Date of Patent: August 16, 2022Assignee: ROHM CO., LTD.Inventors: Shoji Takei, Yuji Koga
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Publication number: 20200312806Abstract: A semiconductor device includes a semiconductor layer having a first surface, an insulating layer formed at the first surface of the semiconductor layer, a Cu conductive layer formed on the insulating layer, the Cu conductive layer made of a metal mainly containing Cu, a second insulating layer formed on the insulating layer, the second insulating layer covering the Cu conductive layer, a Cu pillar extending in a thickness direction in the second insulating layer, the Cu pillar made of a metal mainly containing Cu and electrically connected to the Cu conductive layer, and an intermediate layer formed between the Cu conductive layer and the Cu pillar, the intermediate layer made of a material having a linear expansion coefficient smaller than a linear expansion coefficient of the Cu conductive layer and smaller than a linear expansion coefficient of the Cu pillar.Type: ApplicationFiled: March 27, 2020Publication date: October 1, 2020Applicant: ROHM CO., LTD.Inventors: Shoji TAKEI, Yuji KOGA
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Publication number: 20150338608Abstract: It includes: a first lens having a convex shape on an object side and having positive refractive power; a second lens having a concave shape on an image plane side and having negative refractive power; a third lens having, in a paraxial region, one of a biconvex shape and a plano-convex shape that is provided with a convex surface facing toward the image plane side, the third lens having positive refractive power; a fourth lens having aspherical shapes on both surfaces thereof and having negative refractive power; and a fifth lens having aspherical shapes on both surfaces thereof, having a concave shape in a paraxial region on the image plane side, and having negative refractive power, the first to fifth lenses being arranged in order from the object side. The following conditional expressions are satisfied, where ?2 is an Abbe number of the second lens, and ?4 is an Abbe number of the fourth lens.Type: ApplicationFiled: July 12, 2013Publication date: November 26, 2015Inventor: Shoji TAKEI
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Patent number: 8878294Abstract: An inventive semiconductor device includes a semiconductor layer, a source region provided in a surface layer portion of the semiconductor layer, a drain region provided in the surface of the semiconductor layer in spaced relation from the source region, a gate insulation film provided in opposed relation to a portion of the surface of the semiconductor layer present between the source region and the drain region, a gate electrode provided on the gate insulation film, and a drain-gate isolation portion provided between the drain region and the gate insulation film for isolating the drain region and the gate insulation film from each other in non-contact relation.Type: GrantFiled: July 13, 2013Date of Patent: November 4, 2014Assignee: Rohm Co., Ltd.Inventors: Mitsuo Kojima, Shoji Takei
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Publication number: 20130292765Abstract: An inventive semiconductor device includes a semiconductor layer, a source region provided in a surface layer portion of the semiconductor layer, a drain region provided in the surface of the semiconductor layer in spaced relation from the source region, a gate insulation film provided in opposed relation to a portion of the surface of the semiconductor layer present between the source region and the drain region, a gate electrode provided on the gate insulation film, and a drain-gate isolation portion provided between the drain region and the gate insulation film for isolating the drain region and the gate insulation film from each other in non-contact relation.Type: ApplicationFiled: July 13, 2013Publication date: November 7, 2013Inventors: Mitsuo KOJIMA, Shoji TAKEI
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Patent number: 8520321Abstract: An imaging lens includes an aperture stop, a first lens having positive refractive power, a second lens having negative refractive power, a third lens having positive refractive power, and a fourth lens having negative refractive power. Both surfaces of the first lens, both surfaces of the second lens, both surfaces of the third lens, and both surfaces of the fourth lens are formed as aspheric surfaces. The following condition expression (1), condition expression (2), and condition expression (3) are satisfied. ?1.09?f2/f??0.81??(1) ?1.62?f2/f1??1.42??(2) 0.65?f3/f?0.97??(3) in which f1: the focal length of the first lens f2: the focal length of the second lens f3: the focal length of the third lens f: the focal length of the lens whole system.Type: GrantFiled: August 11, 2011Date of Patent: August 27, 2013Assignee: Sony CorporationInventor: Shoji Takei
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Patent number: 8513766Abstract: An inventive semiconductor device includes a semiconductor layer, a source region provided in a surface layer portion of the semiconductor layer, a drain region provided in the surface of the semiconductor layer in spaced relation from the source region, a gate insulation film provided in opposed relation to a portion of the surface of the semiconductor layer present between the source region and the drain region, a gate electrode provided on the gate insulation film, and a drain-gate isolation portion provided between the drain region and the gate insulation film for isolating the drain region and the gate insulation film from each other in non-contact relation.Type: GrantFiled: June 19, 2008Date of Patent: August 20, 2013Assignee: Rohm Co., Ltd.Inventors: Mitsuo Kojima, Shoji Takei
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Publication number: 20120075723Abstract: An imaging lens includes an aperture stop, a first lens having positive refractive power, a second lens having negative refractive power, a third lens having positive refractive power, and a fourth lens having negative refractive power. Both surfaces of the first lens, both surfaces of the second lens, both surfaces of the third lens, and both surfaces of the fourth lens are formed as aspheric surfaces. The following condition expression (1), condition expression (2), and condition expression (3) are satisfied. ?1.09?f2/f??0.81??(1) ?1.62?f2/f1??1.42??(2) 0.65?f3/f?0.97??(3) in which f1: the focal length of the first lens f2: the focal length of the second lens f3: the focal length of the third lens f: the focal length of the lens whole system.Type: ApplicationFiled: August 11, 2011Publication date: March 29, 2012Applicant: Sony CorporationInventor: Shoji Takei
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Patent number: 6969167Abstract: A soft alumite is produced by forming an oxide film on the surface of an aluminum substrate. Printing is performed on a porous layer formed on the surface of the soft alumite while heating the soft alumite. Alternatively, printing is performed with a dye-based ink on a porous layer formed on the surface of the soft alumite.Type: GrantFiled: September 29, 2004Date of Patent: November 29, 2005Assignee: Seiko Epson CorporationInventors: Yasunori Yamazaki, Shoji Takei
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Publication number: 20050078159Abstract: A soft alumite is produced by forming an oxide film on the surface of an aluminum substrate. Printing is performed on a porous layer formed on the surface of the soft alumite while heating the soft alumite. Alternatively, printing is performed with a dye-based ink on a porous layer formed on the surface of the soft alumite.Type: ApplicationFiled: September 29, 2004Publication date: April 14, 2005Inventors: Yasunori Yamazaki, Shoji Takei
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Patent number: 6808257Abstract: A soft alumite is produced by forming an oxide film on the surface of an aluminum substrate. Printing is performed on a porous layer formed on the surface of the soft alumite while heating the soft alumite. Alternatively, printing is performed with a dye-based ink on a porous layer formed on the surface of the soft alumite.Type: GrantFiled: July 30, 2003Date of Patent: October 26, 2004Assignee: Seiko Epson CorporationInventors: Yasunori Yamazaki, Shoji Takei
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Publication number: 20040021756Abstract: A soft alumite is produced by forming an oxide film on the surface of an aluminum substrate. Printing is performed on a porous layer formed on the surface of the soft alumite while heating the soft alumite. Alternatively, printing is performed with a dye-based ink on a porous layer formed on the surface of the soft alumite.Type: ApplicationFiled: July 30, 2003Publication date: February 5, 2004Inventors: Yasunori Yamazaki, Shoji Takei
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Patent number: 6619793Abstract: A soft alumite is produced by forming an oxide film on the surface of an aluminum substrate. Printing is performed on a porous layer formed on the surface of the soft alumite while heating the soft alumite. Alternatively, printing is performed with a dye-based ink on a porous layer formed on the surface of the soft alumite.Type: GrantFiled: July 3, 2001Date of Patent: September 16, 2003Assignee: Seiko Epson CorporationInventors: Yasunori Yamazaki, Shoji Takei