Patents by Inventor SHOTA HIDA
SHOTA HIDA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11999880Abstract: Provided is a hot melt adhesive sheet comprising a hot melt adhesive that comprises a styrene-based block copolymer and a tackifier, in which the styrene-based block copolymer comprises a hard segment composed of a polystyrene block and a soft segment composed of a constituent unit derived from propylene.Type: GrantFiled: February 20, 2019Date of Patent: June 4, 2024Assignees: NITTO SHINKO CORPORATION, NITTO DENKO CORPORATIONInventors: Kayoko Sasaki, Takafumi Hida, Shota Tanaka
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Publication number: 20240088188Abstract: An imaging device comprises a first chip that includes a first semiconductor substrate including a photoelectric conversion region. The first chip includes a first insulating layer including a first multilayer wiring electrically connected to the photoelectric conversion region. The first multilayer wiring includes a first vertical signal line (VSL1) to output a first pixel signal, and a first wiring. The imaging device includes a second chip including a second semiconductor substrate including a logic circuit. The second chip includes a second insulating layer including a second multilayer wiring electrically connected to the logic circuit. The second multilayer wiring includes a second wiring. The first chip and the second chip are bonded to one another, and, in a plan view, the first wiring and the second wiring overlap with at least a portion of the first vertical signal line (VSL1).Type: ApplicationFiled: September 20, 2023Publication date: March 14, 2024Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hajime YAMAGISHI, Shota HIDA, Yuusaku KOBAYASHI
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Patent number: 11817471Abstract: An imaging device comprises a first chip that includes a first semiconductor substrate including a photoelectric conversion region. The first chip includes a first insulating layer including a first multilayer wiring electrically connected to the photoelectric conversion region. The first multilayer wiring includes a first vertical signal line (VSL1) to output a first pixel signal, and a first wiring. The imaging device includes a second chip including a second semiconductor substrate including a logic circuit. The second chip includes a second insulating layer including a second multilayer wiring electrically connected to the logic circuit. The second multilayer wiring includes a second wiring. The first chip and the second chip are bonded to one another, and, in a plan view, the first wiring and the second wiring overlap with at least a portion of the first vertical signal line (VSL1).Type: GrantFiled: August 27, 2021Date of Patent: November 14, 2023Assignee: Sony Semiconductor Solutions CorporationInventors: Hajime Yamagishi, Shota Hida, Yuusaku Kobayashi
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Publication number: 20230352512Abstract: The present technique relates to an imaging element, an imaging device, and electronic equipment that enable a wiring capacity and a resistance to be reduced. A semiconductor layer in which pixels including photodiodes, first transfer transistors, and second transfer transistors are arranged in a matrix shape and a wiring layer on the semiconductor layer are included, and a first wiring to which the first transfer transistors of the plurality of pixels arranged in a row direction or a column direction from among the pixels are connected and a second wiring to which the second transfer transistors of the plurality of pixels are connected are included on a side of a second surface of the wiring layer that is opposite to a first surface on which the semiconductor layer is laminated. The present technique can be applied to an imaging element that performs distance measurement, for example.Type: ApplicationFiled: June 21, 2021Publication date: November 2, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hajime YAMAGISHI, Shota HIDA
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Publication number: 20220278160Abstract: This technology relates to a solid-state imaging device and an electronic apparatus by which image quality can be enhanced. The solid-state imaging device includes a pixel region in which a plurality of pixels are arranged, a first wiring, a second wiring, and a shield layer. The second wiring is formed in a layer lower than that of the first wiring, and the shield layer is formed in a layer lower at least than that of the first wiring. This technology is applicable to a CMOS image sensor, for example.Type: ApplicationFiled: March 15, 2022Publication date: September 1, 2022Inventors: HAJIME YAMAGISHI, KIYOTAKA TABUCHI, MASAKI OKAMOTO, TAKASHI OINOUE, MINORU ISHIDA, SHOTA HIDA, KAZUTAKA YAMANE
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Patent number: 11289525Abstract: This technology relates to a solid-state imaging device and an electronic apparatus by which image quality can be enhanced. The solid-state imaging device includes a pixel region in which a plurality of pixels are arranged, a first wiring, a second wiring, and a shield layer. The second wiring is formed in a layer lower than that of the first wiring, and the shield layer is formed in a layer lower at least than that of the first wiring. This technology is applicable to a CMOS image sensor, for example.Type: GrantFiled: March 11, 2016Date of Patent: March 29, 2022Assignee: Sony CorporationInventors: Hajime Yamagishi, Kiyotaka Tabuchi, Masaki Okamoto, Takashi Oinoue, Minoru Ishida, Shota Hida, Kazutaka Yamane
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Publication number: 20210391371Abstract: An imaging device comprises a first chip that includes a first semiconductor substrate including a photoelectric conversion region. The first chip includes a first insulating layer including a first multilayer wiring electrically connected to the photoelectric conversion region. The first multilayer wiring includes a first vertical signal line (VSL1) to output a first pixel signal, and a first wiring. The imaging device includes a second chip including a second semiconductor substrate including a logic circuit. The second chip includes a second insulating layer including a second multilayer wiring electrically connected to the logic circuit. The second multilayer wiring includes a second wiring. The first chip and the second chip are bonded to one another, and, in a plan view, the first wiring and the second wiring overlap with at least a portion of the first vertical signal line (VSL1).Type: ApplicationFiled: August 27, 2021Publication date: December 16, 2021Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hajime YAMAGISHI, Shota HIDA, Yuusaku KOBAYASHI
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Patent number: 11133343Abstract: An imaging device comprises a first chip that includes a first semiconductor substrate including a photoelectric conversion region. The first chip includes a first insulating layer including a first multilayer wiring electrically connected to the photoelectric conversion region. The first multilayer wiring includes a first vertical signal line (VSL1) to output a first pixel signal, and a first wiring. The imaging device includes a second chip including a second semiconductor substrate including a logic circuit. The second chip includes a second insulating layer including a second multilayer wiring electrically connected to the logic circuit. The second multilayer wiring includes a second wiring. The first chip and the second chip are bonded to one another, and, in a plan view, the first wiring and the second wiring overlap with at least a portion of the first vertical signal line (VSL1).Type: GrantFiled: May 2, 2018Date of Patent: September 28, 2021Assignee: Sony Semiconductor Solutions CorporationInventors: Hajime Yamagishi, Shota Hida, Yuusaku Kobayashi
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Publication number: 20200243590Abstract: An imaging device comprises a first chip that includes a first semiconductor substrate including a photoelectric conversion region. The first chip includes a first insulating layer including a first multilayer wiring electrically connected to the photoelectric conversion region. The first multilayer wiring includes a first vertical signal line (VSL1) to output a first pixel signal, and a first wiring. The imaging device includes a second chip including a second semiconductor substrate including a logic circuit. The second chip includes a second insulating layer including a second multilayer wiring electrically connected to the logic circuit. The second multilayer wiring includes a second wiring. The first chip and the second chip are bonded to one another, and, in a plan view, the first wiring and the second wiring overlap with at least a portion of the first vertical signal line (VSL1).Type: ApplicationFiled: May 2, 2018Publication date: July 30, 2020Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hajime YAMAGISHI, Shota HIDA, Yuusaku KOBAYASHI
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Publication number: 20180114807Abstract: This technology relates to a solid-state imaging device and an electronic apparatus by which image quality can be enhanced. The solid-state imaging device includes a pixel region in which a plurality of pixels are arranged, a first wiring, a second wiring, and a shield layer. The second wiring is formed in a layer lower than that of the first wiring, and the shield layer is formed in a layer lower at least than that of the first wiring. This technology is applicable to a CMOS image sensor, for example.Type: ApplicationFiled: March 11, 2016Publication date: April 26, 2018Applicant: Sony CorporationInventors: HAJIME YAMAGISHI, KIYOTAKA TABUCHI, MASAKI OKAMOTO, TAKASHI OINOUE, MINORU ISHIDA, SHOTA HIDA, KAZUTAKA YAMANE