Patents by Inventor Shou-Wen Kuo

Shou-Wen Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190164265
    Abstract: A method includes: receiving a defect map from a defect scanner, wherein the defect map comprises at least one defect location of a semiconductor workpiece; annotating the defect map with a reference fiducial location of the semiconductor workpiece; determining a detected fiducial location within image data of the semiconductor workpiece; determining an offset correction based on comparing the detected fiducial location with the reference fiducial location; producing a corrected defect map by applying the offset correction to the defect map, wherein the applying the offset correction translocates the at least one defect location; and transferring the corrected defect map to a defect reviewer configured to perform root cause analysis based on the corrected defect map.
    Type: Application
    Filed: August 21, 2018
    Publication date: May 30, 2019
    Inventors: Chien-Ko Liao, Ya-Hsun Hsueh, Sheng-Hsiang Chuang, Hsu-Shul Liu, Jiun-Rong Pai, Shou-Wen Kuo
  • Publication number: 20190145003
    Abstract: A gas tube, a gas supply system containing the same and a semiconductor manufacturing method using the same are provided. The gas tube includes a porous material body and a resistant sheath surrounding the porous material body. The porous material body has a hollow tube structure and an empty cavity inside the hollow tube structure. The porous material body is hydrophobic and has a plurality of pores therein. The resistant sheath is disposed on the porous material body and surrounds the porous material body. The resistant sheath includes a plurality of holes penetrating through the resistant sheath.
    Type: Application
    Filed: October 28, 2018
    Publication date: May 16, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Shiung Chen, Cheng-Yi Huang, Chih-Shen Yang, Shou-Wen Kuo, Po-Wen Chai
  • Publication number: 20190148187
    Abstract: A detaping machine is adapted for removing a tape from a frame, the tape includes a wafer mounting area and a periphery area surrounding the wafer mounting area. The detaping machine includes a carrier and a detaping module. The carrier is for supporting the tape and the frame. The detaping module includes an elastic pressing device and a detaping head, wherein the periphery area of the tape is adapted to be pressed by the elastic pressing device, and the wafer mounting area of the tape is adapted to be pressed by the detaping head. A detaping method is further provided.
    Type: Application
    Filed: January 22, 2018
    Publication date: May 16, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Sheng Kuo, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo, Wen-Chin Kan, Yang-Ann Chu
  • Patent number: 10283388
    Abstract: A detaping machine is adapted for removing a tape from a frame, the tape includes a wafer mounting area and a periphery area surrounding the wafer mounting area. The detaping machine includes a carrier and a detaping module. The carrier is for supporting the tape and the frame. The detaping module includes an elastic pressing device and a detaping head, wherein the periphery area of the tape is adapted to be pressed by the elastic pressing device, and the wafer mounting area of the tape is adapted to be pressed by the detaping head. A detaping method is further provided.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: May 7, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Sheng Kuo, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo, Wen-Chin Kan, Yang-Ann Chu
  • Publication number: 20190131116
    Abstract: Some embodiments relate to a system. The system includes a radio frequency (RF) generator configured to output a RF signal. A transmission line is coupled to the RF generator. A plasma chamber is coupled to RF generator via the transmission line, wherein the plasma chamber is configured to generate a plasma based on the RF signal. A micro-arc detecting element is configured to determine whether a micro-arc has occurred in the plasma chamber based on the RF signal.
    Type: Application
    Filed: December 26, 2018
    Publication date: May 2, 2019
    Inventors: Feng-Kuang Wu, Chih-Kuo Chang, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo, Sing-Tsung Li
  • Publication number: 20190103314
    Abstract: Some embodiments relate to a processing tool for processing a singulated semiconductor die. The tool includes an evaluation unit, a drying unit, and a die wipe station. The evaluation unit is configured to subject the singulated semiconductor die to a liquid to detect flaws in the singulated semiconductor die. The drying unit is configured to dry the liquid from a frontside of the singulated semiconductor die. The die wipe station includes an absorptive drying structure configured to absorb the liquid from a backside of the singulated semiconductor die after the drying unit has dried the liquid from the frontside of the singulated semiconductor die.
    Type: Application
    Filed: February 23, 2018
    Publication date: April 4, 2019
    Inventors: Tsung-Sheng Kuo, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo, Yang-Ann Chu
  • Publication number: 20190051546
    Abstract: The present disclosure relates to a method of automatically re-programming an EFEM to account for positional changes of the EFEM robot. In some embodiments, the method is performed by determining an initial position of an EFEM robot within an EFEM chamber. The EFEM robot at the initial position moves along a first plurality of steps defined relative to the initial position and that extend along a path between a first position and a second position. Positional parameters are determined, which describe a change between an initial position and a new position of the EFEM robot that is different than the initial position. A second plurality of steps are determined based upon the positional parameters. The EFEM robot at the new position moves along the second plurality of steps defined relative to the new position and that extend along the path between the first position and the second position.
    Type: Application
    Filed: November 27, 2017
    Publication date: February 14, 2019
    Inventors: Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo
  • Publication number: 20190035696
    Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.
    Type: Application
    Filed: February 26, 2018
    Publication date: January 31, 2019
    Inventors: Chia-Han Lin, Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Surendra Kumar Soni, Shou-Wen Kuo, Wu-An Weng, Gary Tsai, Chien-Ko Liao, Ya Hsun Hsueh, Becky Liao, Ethan Yu, Ming-Chi Tsai, Kuo-Yi Liu
  • Publication number: 20190019760
    Abstract: A wafer includes a first face having a first center, and a second face having a second center. The first and second centers are each arranged on a central axis, which passes through the first face and the second face. The first face and the second face adjoin one another at a circumferential edge. An alignment notch is disposed along the circumferential edge, and extends inwardly from the circumferential edge by an alignment notch radial distance. The alignment notch radial distance is less than a wafer radius as measured from the first center to the circumferential edge. A die region includes an array of die arranged in rows and columns and is circumferentially bounded by a die-less region which is devoid of die. A first identification mark including a string of characters is disposed entirely in the die-less region to a first side of the alignment notch.
    Type: Application
    Filed: February 26, 2018
    Publication date: January 17, 2019
    Inventors: Yue-Lin Peng, Cheng-Yi Huang, Fu-Jen Li, Shou-Wen Kuo
  • Patent number: 10170287
    Abstract: Some embodiments relate to a system. The system includes a radio frequency (RF) generator configured to output a RF signal. A transmission line is coupled to the RF generator. A plasma chamber is coupled to RF generator via the transmission line, wherein the plasma chamber is configured to generate a plasma based on the RF signal. A micro-arc detecting element is configured to determine whether a micro-arc has occurred in the plasma chamber based on the RF signal.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng-Kuang Wu, Chih-Kuo Chang, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo, Sing-Tsung Li
  • Publication number: 20180366357
    Abstract: A system and method for inline detection of defects on a semiconductor wafer surface during a semiconductor device manufacturing process is disclosed herein. In one embodiment, a method includes: automatically transporting the wafer from a first processing station to an inspection station; scanning a wafer surface using a camera in the inspection station; generating at least one image of the wafer surface; analyzing the at least one image to detect defects on the wafer surface based on a set of predetermined criteria; if the wafer is determined to be defective, automatically transporting the wafer from the inspection station to a stocker; and if the wafer is determined to be not defective, automatically transporting the wafer to a second processing station for further processing in accordance with the semiconductor device manufacturing process.
    Type: Application
    Filed: August 8, 2018
    Publication date: December 20, 2018
    Inventors: Chien-Ko LIAO, Hsu-Shui LIU, Jiun-Rong PAI, Sheng-Hsiang CHUANG, Shou-Wen KUO, Ya Hsun HSUEH
  • Publication number: 20170372932
    Abstract: The present disclosure relates to an integrated chip (IC) processing tool having a die exchanger configured to automatically transfer a plurality of IC die between a die tray and a die boat, and an associated method. The integrated chip processing tool has a die exchanger configured to receive a die tray comprising a plurality of IC die. The die exchanger is configured to automatically transfer the plurality of IC die between the die tray and a die boat. An IC die processing tool is configured to receive the die boat from the die exchanger and to perform a processing step on the plurality of IC die within the die boat. By operating the die exchanger to automatically transfer IC die between the die tray and the die boat, the transfer time can be reduced and contamination and/or damage risks related to a manual transfer of IC die can be mitigated.
    Type: Application
    Filed: August 29, 2016
    Publication date: December 28, 2017
    Inventors: Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Pin-Yi Hsin, Shou-Wen Kuo, Patrick Lin
  • Patent number: 9852936
    Abstract: A load port for a processing tool includes a carrier, a carrier actuator, an input table, an input table actuator, and a controller. The carrier has a plurality of cassette buffering spaces. The carrier is movable relative to the processing tool. The carrier actuator is operably connected to the carrier. The input table is configured to receive at least one cassette. The input table is movable relative to the carrier. The input table actuator is operably connected to the input table. The controller is configured to control the carrier actuator to move the carrier, such that one of the cassette buffering spaces is aligned with the input table, configured to control the input table actuator to move the input table with the cassette into the aligned cassette buffering space, and configured to control the input table to load the cassette into the aligned cassette buffering space.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: December 26, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo
  • Patent number: 9786530
    Abstract: A wafer transfer method includes the following steps. An initial position of a first wafer in a wafer cassette is detected. A picking entry position in the wafer cassette is determined based on the initial position of the first wafer, in which the picking entry position is spaced apart from the initial position of the first wafer. A wafer transfer blade is moved to the picking entry position.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: October 10, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo
  • Patent number: 9460957
    Abstract: An isolation feature with a nitrogen-doped fill dielectric and a method of forming the isolation feature are disclosed. In an exemplary embodiment, the method of forming the isolation feature comprises receiving a substrate having a top surface. A recess is etched in the substrate, the recess extending from the top surface into the substrate. A dielectric is deposited within the recess such that the depositing of the dielectric includes introducing nitrogen during a chemical vapor deposition process. Accordingly, the deposited dielectric includes a nitrogen-doped dielectric. The deposited dielectric may include a nitrogen-doped silicon oxide. In some embodiments, the depositing of the dielectric disposes the nitrogen-doped dielectric in contact with a surface of the recess. In further embodiments, a liner material is deposited within the recess prior to the depositing of the dielectric within the recess.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: October 4, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shing Long Lee, Yi-Chieh Wang, Chung-Han Lin, Kuang-Jung Peng, Yun Chang, Shou-Wen Kuo
  • Publication number: 20160225649
    Abstract: A load port for a processing tool includes a carrier, a carrier actuator, an input table, an input table actuator, and a controller. The carrier has a plurality of cassette buffering spaces. The carrier is movable relative to the processing tool. The carrier actuator is operably connected to the carrier. The input table is configured to receive at least one cassette. The input table is movable relative to the carrier. The input table actuator is operably connected to the input table. The controller is configured to control the carrier actuator to move the carrier, such that one of the cassette buffering spaces is aligned with the input table, configured to control the input table actuator to move the input table with the cassette into the aligned cassette buffering space, and configured to control the input table to load the cassette into the aligned cassette buffering space.
    Type: Application
    Filed: January 29, 2015
    Publication date: August 4, 2016
    Inventors: Chien-Fa LEE, Hsu-Shui LIU, Jiun-Rong PAI, Shou-Wen KUO
  • Publication number: 20160111311
    Abstract: A wafer transfer method includes the following steps. An initial position of a first wafer in a wafer cassette is detected. A picking entry position in the wafer cassette is determined based on the initial position of the first wafer, in which the picking entry position is spaced apart from the initial position of the first wafer. A wafer transfer blade is moved to the picking entry position.
    Type: Application
    Filed: October 20, 2014
    Publication date: April 21, 2016
    Inventors: Chien-Fa LEE, Hsu-Shui LIU, Jiun-Rong PAI, Shou-Wen KUO
  • Publication number: 20140264720
    Abstract: An isolation feature with a nitrogen-doped fill dielectric and a method of forming the isolation feature are disclosed. In an exemplary embodiment, the method of forming the isolation feature comprises receiving a substrate having a top surface. A recess is etched in the substrate, the recess extending from the top surface into the substrate. A dielectric is deposited within the recess such that the depositing of the dielectric includes introducing nitrogen during a chemical vapor deposition process. Accordingly, the deposited dielectric includes a nitrogen-doped dielectric. The deposited dielectric may include a nitrogen-doped silicon oxide. In some embodiments, the depositing of the dielectric disposes the nitrogen-doped dielectric in contact with a surface of the recess. In further embodiments, a liner material is deposited within the recess prior to the depositing of the dielectric within the recess.
    Type: Application
    Filed: September 9, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shing Long Lee, Yi-Chieh Wang, Chung-Han Lin, Kuang-Jung Peng, Yun Chang, Shou-Wen Kuo