Patents by Inventor Shougo Hayashi
Shougo Hayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 6724452Abstract: A vertical alignment mode liquid crystal display device having an improved viewing angle characteristic is provided. The liquid crystal display device uses a liquid crystal having a negative anisotropic dielectric constant, and orientations of the liquid crystal are vertical to substrates when no voltage is applied, almost horizontal when a predetermined voltage is applied, and oblique when an intermediate voltage is applied. At least one of the substrates includes a structure as domain regulating means, and inclined surfaces of the structure operate as a trigger to regulate azimuths of the oblique orientations of the liquid crystal when the intermediate voltage is applied.Type: GrantFiled: June 12, 1998Date of Patent: April 20, 2004Assignee: Fujitsu Display Technologies CorporationInventors: Arihiro Takeda, Katsufumi Ohmuro, Yoshio Koike, Shingo Kataoka, Takahiro Sasaki, Takashi Sasabayashi, Hideaki Tsuda, Hideo Chida, Makoto Ohashi, Kenji Okamoto, Hisashi Yamaguchi, Minoru Otani, Makoto Morishige, Noriaki Furukawa, Tsuyoshi Kamada, Yoshinori Tanaka, Atuyuki Hoshino, Shougo Hayashi, Hideaki Takizawa, Takeshi Kinjou, Makoto Tachibanaki, Keiji Imoto, Tadashi Hasegawa, Hidefumi Yoshida, Hiroyasu Inoue, Yoji Taniguchi, Tetsuya Fujikawa, Satoshi Murata, Manabu Sawasaki, Tomonori Tanose, Siro Hirota, Masahiro Ikeda, Kunihiro Tashiro, Kouji Tsukao, Yasutoshi Tasaka, Takatoshi Mayama, Seiji Tanuma, Yohei Nakanishi
-
Publication number: 20040046175Abstract: A TFT matrix-type liquid crystal display device is used in laptop personal computers and wall TVs. On a transparent insulating substrate 10 there are formed gate bus lines 14 for commonly connecting the gates of thin film transistors, drain bus lines 16 for commonly connecting the drains of the thin film transistors, and outside terminals 20 and outside terminals 30 opposed respectively to the ends of the gate bus lines and the drain bus lines 16, opposed respectively to the ends of the gate bus lines and the drain bus lines. Gate connection lines 24 for commonly connecting the gate bus lines 14 and drain connection lines 34 for commonly connecting the drain bus lines are formed in regions inner of the outside terminals 20, 30. The thin film transistor matrix device can be fabricated without occurrence of short circuit defects, with little characteristic change and with high yields.Type: ApplicationFiled: September 11, 2003Publication date: March 11, 2004Applicant: FUJITSU DISPLAY TECHNOLOGIES CORPORATIONInventors: Hideaki Takizawa, Shougo Hayashi, Takeshi Kinjo, Makoto Tachibanaki, Kenji Okamoto
-
Patent number: 6661488Abstract: A vertically alignment mode liquid crystal display device having an improved viewing angle characteristic is disclosed. The disclosed liquid crystal display device uses a liquid crystal having a negative anisotropic dielectric constant, and orientations of the liquid crystal are vertical to substrates when no voltage being applied, almost horizontal when a predetermined voltage is applied, and oblique when an intermediate voltage is applied. At least one of the substrates includes a structure as domain regulating means, and inclined surfaces of the structure operate as a trigger to regulate azimuths of the oblique orientations of the liquid crystal when the intermediate voltage is applied.Type: GrantFiled: September 18, 2000Date of Patent: December 9, 2003Assignee: Fujitsu LimitedInventors: Arihiro Takeda, Katsufumi Ohmuro, Yoshio Koike, Shingo Kataoka, Takahiro Sasaki, Takashi Sasabayashi, Hideaki Tsuda, Hideo Chida, Makoto Ohashi, Kenji Okamoto, Hisashi Yamaguchi, Minoru Otani, Makoto Morishige, Noriaki Furukawa, Tsuyoshi Kamada, Yoshinori Tanaka, Atuyuki Hoshino, Shougo Hayashi, Hideaki Takizawa, Takeshi Kinjou, Makoto Tachibanaki, Keiji Imoto, Tadashi Hasegawa, Hidefumi Yoshida, Hiroyasu Inoue, Yoji Taniguchi, Tetsuya Fujikawa, Satoshi Murata, Manabu Sawasaki, Tomonori Tanose, Siro Hirota, Masahiro Ikeda, Kunihiro Tashiro, Kouji Tsukao, Yasutoshi Tasaka, Takatoshi Mayama, Seiji Tanuma, Yohei Nakanishi
-
Publication number: 20030067038Abstract: A conductive film made of Al or alloy containing Al as a main component is formed on an underlying substrate. An upper conductive film is disposed on the conductive film. A first opening is formed through the upper conductive film. An insulating film is disposed on the upper conductive film. A second opening is formed through the insulating film. An inner wall of the second opening is retreated from an inner wall of the first opening. An ITO film is formed covering a partial upper surface of the insulating film and inner surfaces of the first and second openings, and contacting a partial upper surface of the upper conductive film at a region inside of the second opening. Good electrical contact between an Al or Al alloy film and an ITO film can be established and productivity can be improved.Type: ApplicationFiled: November 12, 2002Publication date: April 10, 2003Applicant: Fujitsu LimitedInventors: Tetsuya Fujikawa, Hidetoshi Sukenori, Shougo Hayashi, Yoshinori Tanaka, Masahiro Kihara
-
Patent number: 6509215Abstract: A conductive film made of Al or alloy containing Al as a main component is formed on an underlying substrate. An upper conductive film is disposed on the conductive film. A first opening is formed through the upper conductive film. An insulating film is disposed on the upper conductive film. A second opening is formed through the insulating film. An inner wall of the second opening is retreated from an inner wall of the first opening. An ITO film is formed covering a partial upper surface of the insulating film and inner surfaces of the first and second openings, and contacting a partial upper surface of the upper conductive film at a region inside of the second opening. Good electrical contact between an Al or Al alloy film and an ITO film can be established and productivity can be improved.Type: GrantFiled: August 9, 2001Date of Patent: January 21, 2003Assignee: Fujitsu LimitedInventors: Tetsuya Fujikawa, Hidetoshi Sukenori, Shougo Hayashi, Yoshinori Tanaka, Masahiro Kihara
-
Publication number: 20020084460Abstract: A TFT matrix-type liquid crystal display device is used in laptop personal computers and wall TVs. On a transparent insulating substrate 10 there are formed gate bus lines 14 for commonly connecting the-gates of thin film transistors, drain bus lines 16 for commonly connecting the drains of the thin film transistors, and outside terminals 20 and outside terminals 30 opposed respectively to the ends of the gate bus lines and the drain bus lines 16, opposed respectively to the ends of the gate bus lines and the drain bus lines. Gate connection lines 24 for commonly connecting the gate bus lines 14 and drain connection lines 34 for commonly connecting the drain bus lines are formed in regions inner of the outside terminals 20, 30. The thin film transistor matrix device can be fabricated without occurrence of short circuit defects, with little characteristic change and with high yields.Type: ApplicationFiled: February 21, 2002Publication date: July 4, 2002Applicant: FUJITSU LIMITEDInventors: Hidaki Takizawa, Shougo Hayashi, Takeshi Kinjo, Makoto Tachibanaki, Kenji Okamoto
-
Patent number: 6406946Abstract: A TFT matrix-type liquid crystal display device is used in laptop personal computers and wall TV's. On a transparent insulating substrate there are formed gate bus lines for commonly connecting the gates of thin film transistors, drain bus lines for commonly connecting the drains of the thin film transistors, and outside terminals and outside terminals opposed respectively to the ends of the gate bus lines and the drain bus lines, opposed respectively to the ends of the gate bus lines and the drain bus lines. Gate connection lines for commonly connecting the gate bus lines and drain connection lines for commonly connecting the drain bus lines are formed on the transparent insulating substrate in regions inner of the outside terminals. The thin film transistor matrix device can be fabricated without occurrence of short circuit defects, with little characteristic change and with high yields.Type: GrantFiled: January 8, 1998Date of Patent: June 18, 2002Assignee: Fujitsu LimitedInventors: Hidaki Takizawa, Shougo Hayashi, Takeshi Kinjo, Makoto Tachibanaki, Kenji Okamoto
-
Publication number: 20020028540Abstract: A TFT matrix-type liquid crystal display device is used in laptop personal computers and wall TVs. On a transparent insulating substrate 10 there are formed gate bus lines 14 for commonly connecting the gates of thin film transistors, drain bus lines 16 for commonly connecting the drains of the thin film transistors, and outside terminals 20 and outside terminals 30 opposed respectively to the ends of the gate bus lines and the drain bus lines 16, opposed respectively to the ends of the gate bus lines and the drain bus lines. Gate connection lines 24 for commonly connecting the gate bus lines 14 and drain connection lines 34 for commonly connecting the drain bus lines are formed in regions inner of the outside terminals 20, 30. The thin film transistor matrix device can be fabricated without occurrence of short circuit defects, with little characteristic change and with high yields.Type: ApplicationFiled: January 8, 1998Publication date: March 7, 2002Inventors: HIDAKI TAKIZAWA, SHOUGO HAYASHI, TAKESHI KINJO, MAKOTO TACHIBANAKI, KENJI OKAMOTO
-
Publication number: 20020000555Abstract: A conductive film made of Al or alloy containing Al as a main component is formed on an underlying substrate. An upper conductive film is disposed on the conductive film. A first opening is formed through the upper conductive film. An insulating film is disposed on the upper conductive film. A second opening is formed through the insulating film. An inner wall of the second opening is retreated from an inner wall of the first opening. An ITO film is formed covering a partial upper surface of the insulating film and inner surfaces of the first and second openings, and contacting a partial upper surface of the upper conductive film at a region inside of the second opening. Good electrical contact between an Al or Al alloy film and an ITO film can be established and productivity can be improved.Type: ApplicationFiled: August 9, 2001Publication date: January 3, 2002Applicant: Fujitsu LimitedInventors: Tetsuya Fujikawa, Hidetoshi Sukenori, Shougo Hayashi, Yoshinori Tanaka, Masahiro Kihara
-
Patent number: 6297519Abstract: A conductive film made of Al or alloy containing Al as a main component is formed on an underlying substrate. An upper conductive film is disposed on the conductive film. A first opening is formed through the upper conductive film. An insulating film is disposed on the upper conductive film. A second opening is formed through the insulating film. An inner wall of the second opening is retreated from an inner wall of the first opening. An ITO film is formed covering a partial upper surface of the insulating film and inner surfaces of the first and second openings, and contacting a partial upper surface of the upper conductive film at a region inside of the second opening. Good electrical contact between an Al or Al alloy film and an ITO film can be established and productivity can be improved.Type: GrantFiled: April 23, 1999Date of Patent: October 2, 2001Assignee: Fujitsu LimitedInventors: Tetsuya Fujikawa, Hidetoshi Sukenori, Shougo Hayashi, Yoshinori Tanaka, Masahiro Kihara
-
Patent number: 5795686Abstract: A pattern forming method of forming an overall pattern by connecting a plurality of pattern forming regions. The pattern forming method includes the steps of (A) forming, using a first exposure mask (RT11a), a plurality of latent images of first patterns arranged regularly in a photosensitive resist film (52) on a first region while forming unexposed regions having a size in which one or more of the first patterns are included and latent images of the first patterns in it on a third region (JT1), and (B) forming, using a second exposure mask (RT11b), a plurality of latent images of the first patterns arranged regularly in the photosensitive resist film (52) on a second region while forming latent images of the first patterns in the unexposed regions on the third region (JT1).Type: GrantFiled: December 19, 1996Date of Patent: August 18, 1998Assignee: Fujitsu LimitedInventors: Hideaki Takizawa, Shougo Hayashi
-
Patent number: 5742074Abstract: A TFT matrix-type liquid crystal display device is used in laptop personal coputers and wall TV's. On a transparent insulating substrate there are formed gate bus lines for commonly connecting the gates of thin film transistors, drain bus lines for commonly connecting the drains of the thin film transistors, and outside terminals and outside terminals opposed respectively to the ends of the gate bus lines and the drain bus lines, opposed respectively to the ends of the gate bus lines and the drain bus lines. Gate connection lines for commonly connecting the gate bus lines and drain connection lines for commonly connecting the drain bus lines are formed on the transparent insulating substrate in regions inner of the outside terminals. The thin film transistor matrix device can be fabricated without occurrence of short circuit defects, with little characteristic change and with high yields.Type: GrantFiled: May 29, 1996Date of Patent: April 21, 1998Assignee: Fujitsu LimitedInventors: Hidaki Takizawa, Shougo Hayashi, Takeshi Kinjo, Makoto Tachibanaki, Kenji Okamoto