Abstract: A system for clock calibration is described herein which comprises a serializer configured to convert an input data stream in parallel format to provide an out data stream in a serial format; a clock source configured to generate one or more clock signals; a first frequency divider configured to provide at least one divided clock signal of the one or more clock signals; a delay line configured to delay at least one divided clock signal; and a clock calibrator configured to control delay of the at least one divided clock signal at the delay line to adjust the one or more divided clock signals at a fixed relationship with respect to the one or more clock signals based on voltage and temperature variation.

Abstract: A system for clock calibration is described herein which comprises a serializer configured to convert an input data stream in parallel format to provide an out data stream in a serial format; a clock source configured to generate one or more clock signals; a first frequency divider configured to provide at least one divided clock signal of the one or more clock signals; a delay line configured to delay at least one divided clock signal; and a clock calibrator configured to control delay of the at least one divided clock signal at the delay line to adjust the one or more divided clock signals at a fixed relationship with respect to the one or more clock signals based on voltage and temperature variation.

Abstract: A duty cycle correction (DCC) circuit includes first and second pluralities of logic gates, a low pass filter, an error amplifier, and a differential amplifier. The DCC circuit receives first and second clock signals from the VCO. The first and second pluralities of logic gates receive first and second superimposed clock signals and generate first and second output clock signals, respectively. The error amplifier rectifies a common error of the first and second output clock signals, and generates a common mode error voltage signal. The differential amplifier generates first and second error signals based on the common mode error voltage signal. The first and second error signals converge the duty cycles of the first and second output clock signals to a 50% duty cycle.