Patents by Inventor Shreesh Narasimha

Shreesh Narasimha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Asymmetric high-K dielectric for reducing gate induced drain leakage
    Patent number: 9577061
    Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: February 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony I. Chou, Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw
  • Asymmetric high-K dielectric for reducing gate induced drain leakage
    Patent number: 9570354
    Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: February 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony I. Chou, Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw
  • Asymmetric high-k dielectric for reducing gate induced drain leakage
    Patent number: 9559010
    Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: January 31, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony I. Chou, Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw
  • Asymmetric high-k dielectric for reducing gate induced drain leakage
    Patent number: 9543213
    Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: January 10, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony I. Chou, Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw
  • SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE STRUCTURES
    Publication number: 20160307918
    Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.
    Type: Application
    Filed: June 29, 2016
    Publication date: October 20, 2016
    Inventors: Anthony I. Chou, Arvind Kumar, Renee T. Mo, Shreesh Narasimha
  • SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE STRUCTURES
    Publication number: 20160307806
    Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.
    Type: Application
    Filed: June 29, 2016
    Publication date: October 20, 2016
    Inventors: Anthony I. Chou, Arvind Kumar, Renee T. Mo, Shreesh Narasimha
  • ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE
    Publication number: 20160268390
    Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
    Type: Application
    Filed: May 19, 2016
    Publication date: September 15, 2016
    Inventors: Anthony I. CHOU, Arvind KUMAR, Chung-Hsun LIN, Shreesh NARASIMHA, Claude ORTOLLAND, Jonathan T. SHAW
  • Shallow trench isolation structure having a nitride plug
    Patent number: 9443929
    Abstract: A semiconductor structure and method for forming a shallow trench isolation (STI) structure having one or more oxide layers and a nitride plug. Specifically, the structure and method involves forming one or more trenches in a substrate. The STI structure is formed having one or more oxide layers and a nitride plug, wherein the STI structure is formed on and adjacent to at least one of the one or more trenches. One or more gates are formed on the substrate and spaced at a distance from each other. A dielectric layer is formed on and adjacent to the substrate, the STI structure, and the one or more gates.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: September 13, 2016
    Assignee: International Business Machines Corporation
    Inventors: Byeong Y. Kim, Shreesh Narasimha
  • ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE
    Publication number: 20160260618
    Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
    Type: Application
    Filed: May 19, 2016
    Publication date: September 8, 2016
    Inventors: Anthony I. CHOU, Arvind KUMAR, Chung-Hsun LIN, Shreesh NARASIMHA, Claude ORTOLLAND, Jonathan T. SHAW
  • ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE
    Publication number: 20160260638
    Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
    Type: Application
    Filed: May 19, 2016
    Publication date: September 8, 2016
    Inventors: Anthony I. CHOU, Arvind KUMAR, Chung-Hsun LIN, Shreesh NARASIMHA, Claude ORTOLLAND, Jonathan T. SHAW
  • Merged source drain epitaxy
    Patent number: 9437496
    Abstract: A semiconductor device such as a FinFET includes a plurality of fins formed upon a substrate and a gate covering a portion of the fins. Diamond-shaped volumes are formed on the sidewalls of the fins by epitaxial growth which may be limited to avoid merging of the volumes or where the epitaxy volumes have merged. Because of the difficulties in managing merging of the diamond-shaped volumes, a controlled merger of the diamond-shaped volumes includes depositing an amorphous semiconductor material upon the diamond-shaped volumes and a crystallization process to crystallize the deposited semiconductor material on the diamond-shaped volumes to fabricate controllable and uniformly merged source drain.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: September 6, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Michael P. Chudzik, Brian J. Greene, Edward P. Maciejewski, Kevin McStay, Shreesh Narasimha, Chengwen Pei, Werner A. Rausch
  • Semiconductor structure with integrated passive structures
    Patent number: 9425079
    Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: August 23, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony I. Chou, Arvind Kumar, Renee T. Mo, Shreesh Narasimha
  • Asymmetric high-k dielectric for reducing gate induced drain leakage
    Patent number: 9412667
    Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: August 9, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony I. Chou, Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw
  • Planar polysilicon regions for precision resistors and electrical fuses and method of fabrication
    Patent number: 9401325
    Abstract: A semiconductor structure providing a precision resistive element and method of fabrication is disclosed. Polysilicon is embedded in a silicon substrate. The polysilicon may be doped to control the resistance. Embodiments may include resistors, eFuses, and silicon-on-insulator structures. Some embodiments may include non-rectangular cross sections.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: July 26, 2016
    Assignee: International Business Machine Corporation
    Inventors: Anthony I-Chih Chou, Arvind Kumar, Renee T. Mo, Shreesh Narasimha
  • ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE
    Publication number: 20160204214
    Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
    Type: Application
    Filed: March 21, 2016
    Publication date: July 14, 2016
    Inventors: Anthony I. CHOU, Arvind KUMAR, Chung-Hsun LIN, Shreesh NARASIMHA, Claude ORTOLLAND, Jonathan T. SHAW
  • ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE
    Publication number: 20160203987
    Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
    Type: Application
    Filed: March 21, 2016
    Publication date: July 14, 2016
    Inventors: Anthony I. CHOU, Arvind KUMAR, Chung-Hsun LIN, Shreesh NARASIMHA, Claude ORTOLLAND, Jonathan T. SHAW
  • ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE
    Publication number: 20160204209
    Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
    Type: Application
    Filed: March 21, 2016
    Publication date: July 14, 2016
    Inventors: Anthony I. CHOU, Arvind KUMAR, Chung-Hsun LIN, Shreesh NARASIMHA, Claude ORTOLLAND, Jonathan T. SHAW
  • ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE
    Publication number: 20160203985
    Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
    Type: Application
    Filed: March 21, 2016
    Publication date: July 14, 2016
    Inventors: Anthony I. CHOU, Arvind KUMAR, Chung-Hsun LIN, Shreesh NARASIMHA, Claude ORTOLLAND, Jonathan T. SHAW
  • ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE
    Publication number: 20160203986
    Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
    Type: Application
    Filed: March 21, 2016
    Publication date: July 14, 2016
    Inventors: Anthony I. CHOU, Arvind KUMAR, Chung-Hsun LIN, Shreesh NARASIMHA, Claude ORTOLLAND, Jonathan T. SHAW
  • ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE
    Publication number: 20160149013
    Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
    Type: Application
    Filed: November 25, 2014
    Publication date: May 26, 2016
    Inventors: Anthony I. CHOU, Arvind KUMAR, Chung-Hsun LIN, Shreesh NARASIMHA, Claude ORTOLLAND, Jonathan T. SHAW