Abstract: The present disclosure relates to the field of switch gears, and envisages an actuator for a switch gear of an electric panel having a door. The actuator comprises an aligner assembly and an actuator plate assembly. The aligner assembly comprises an aligner pivotably mounted on the switch gear housing, and engaging with a toggle of a circuit breaker, of the switch gear, to angularly displace the toggle. The aligner has a pair of slanting flanges configured to define a valley separated by a gap. The actuator plate assembly comprises a mounting plate mounted on the enclosure door. A shaft element, having a handle element and an engaging element, passes through the mounting plate. The engaging element is configured to nest in the gap of the aligner to angularly displace the aligner.

Abstract: A self-biased differential transmitter is provided. The transmitter may include a differential output driver powered by a supply voltage provided by a differential signal receiver. The output driver may include a bias voltage generator to generate bias voltages to enable one or more transistors in the output driver to operate with differential signals that are beyond the safe operating voltage range of transistors included within the differential transmitter.

Abstract: Display devices with improved routing between connectors and source drivers disposed on a substrate such as glass. Various features improve different characteristics of the routings between the connectors and source drivers. For example, a t-shaped connector is provided to ensure voltage provided to the source drivers is approximately equal. Routings may be tapered (i.e., altered in width) to reduce the amount of area consumption in locations where doing so is desirable but to decrease resistance in areas having more space. Routings may also include stacked power supply and ground traces to provide benefits such as improved decoupling capacitance. Other features are provided.

Abstract: A Method and Apparatus for a Transmission Gate for Multi-GB/s Application have been disclosed. By actively biasing the gate and body of both NFET and PFET improved performance is achieved.

Abstract: This disclosure generally provides a processing system that includes a first controller coupled with a second controller via a first communication link. The first controller is configured to transmit display data and configuration data to the second controller via the first communication link. The second controller is configured to drive, using the display data, one or more coupled display electrodes for performing display updating. The second controller is further configured to operate one or more coupled sensor electrodes using the configuration data to acquire capacitive sensing data, and to transmit the capacitive sensing data to the first controller via the first communication link.

Abstract: This disclosure generally provides a processing system that includes a first controller coupled with a second controller via a first communication link. The first controller is configured to transmit display data and configuration data to the second controller via the first communication link. The second controller is configured to drive, using the display data, one or more coupled display electrodes for performing display updating. The second controller is further configured to operate one or more coupled sensor electrodes using the configuration data to acquire capacitive sensing data, and to transmit the capacitive sensing data to the first controller via the first communication link.

Abstract: Display devices with improved routing between connectors and source drivers disposed on a substrate such as glass. Various features improve different characteristics of the routings between the connectors and source drivers. For example, a t-shaped connector is provided to ensure voltage provided to the source drivers is approximately equal. Routings may be tapered (i.e., altered in width) to reduce the amount of area consumption in locations where doing so is desirable but to decrease resistance in areas having more space. Routings may also include stacked power supply and ground traces to provide benefits such as improved decoupling capacitance. Other features are provided.

Abstract: A data receiver identifies an alignment symbol in a parallel data stream including encoded symbols, generates a bit order indicator indicating a bit order of the alignment symbol identified in the parallel data stream, and generates a symbol stream including the encoded symbols. Further, the data receiver decodes symbols in the symbol stream and generates a bit polarity indicator indicating a bit polarity of the parallel data stream based on the decoded symbols. Additionally, the data receiver generates a formatted symbol stream having a predetermined bit order and a predetermined bit polarity, based on the symbol stream, the bit order indicator, and the bit polarity indicator. In some embodiments, the data receives a serial data stream and generates the parallel data stream by deserializing data in the serial data stream.

Abstract: Novel, stable formulations of bupropion hydrochloride are provided which will maintain at least 80% of initial bupropion hydrochloride potency after one year. Methods of inhibiting degradation of bupropion hydrochloride and methods of preparing stable formulations of bupropion hydrochloride are also provided.

Abstract: A high-speed, compact, edge-triggered flip-flop circuit is provided which includes an input circuit section, a latch circuit section and an output circuit section. The input circuit section includes at least one transistor such as a field-effect transistor (FET) which determines the logic function of the flip-flop such as D, S-R, or T, and provides a first stage of latching. The input circuit section receives the logic control signals such as D, S-R, or T, and a clock signal. In one embodiment of the invention, the latch circuit section includes two series-connected negative differential resistance (NDR) diodes. In this embodiment, a common terminal of the two NDR diodes is connected to the data output of the input circuit section and to the data input of the output circuit section.

Abstract: Novel, stable formulations of bupropion hydrochloride are provided which will maintain at least 80% of initial bupropion hydrochloride potency after one year. Methods of inhibiting degradation of bupropion hydrochloride and methods of preparing stable formulations of bupropion hydrochloride are also provided.

Abstract: Novel, stable formulations of bupropion hydrochloride are provided which will maintain at least 80% of initial bupropion hydrochloride potency after one year. Methods of inhibiting degradation of bupropion hydrochloride and methods of preparing stable formulations of bupropion hydrochloride are also provided.

Abstract: Novel, stable formulations of bupropion hydrochloride are provided which will maintain at least 80% of initial bupropion hydrochloride potency after one year. Methods of inhibiting degradation of bupropion hydrochloride and methods of preparing stable formulations of bupropion hydrochloride are also provided.

Abstract: Novel, stable formulations of bupropion hydrochloride are provided which will maintain at least 80% of initial bupropion hydrochloride potency after one year. Methods of inhibiting degradation of bupropion hydrochloride are also provided.

Abstract: A digital logic gate circuit including a logic block, clock transistor, bias transistor and a negative differential resistance (NDR) diode which acts as an active load for the circuit. The logic block, comprising a plurality of field effect transistors whose control terminals receive the set of input signals to the logic gate, determines the gate function such as inversion, NAND, NOR, MAJORITY, etc. The clock transistor is connected in series with the logic block and the bias transistor is connected in parallel across this series combination. The terminal of the NDR diode affixed to the common terminal of the bias transistor and the logic block forms the output for the logic circuit. NDR diodes include but are not limited to devices such as tunnel diodes and resonant tunneling diodes (RTDs). The folded I-V characteristic of an NDR diode allows the circuits to operate in a bistable clocked mode, where the circuit output latches its state and changes only when the clock signal is active.