Patents by Inventor Shu Chen

Shu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240119471
    Abstract: According to the embodiments of the present disclosure, a method for conversion evaluation comprises: extracting a resource feature from resource-related data of a target resource; extracting an audience feature of the target audience group from audience-related data of a target audience group of the target resource, the target audience group being to be distributed with a recommended content item related to the target resource; and determining, based on the resource feature and the audience feature, a target predicted conversion rate for the target resource through a predetermined association between resource features, audience features and predicted conversion rates, the target predicted conversion rate indicating a predicted probability of the target audience group performing a conversion for the target resource. According to the scheme, the accuracy of the conversion rate evaluation may be improved, thereby improving distribution effect of the recommended content item for a resource.
    Type: Application
    Filed: September 22, 2023
    Publication date: April 11, 2024
    Inventors: Xiaowang Kong, Shu Chen, Zhibin Wu, Zhe Wang, Haiqian HE
  • Patent number: 11956421
    Abstract: Method and apparatus of video coding are disclosed. According to one method, in the decoder side, a predefined Intra mode is assigned to a neighboring block adjacent to the current luma block when the neighboring block satisfies one or more conditions. An MPM (Most Probable Mode) list is derived based on information comprising at least one of neighboring Intra modes. A current Intra mode is derived utilizing the MPM list. The current luma block is decoded according to the current Intra mode According to another method, a predefined Intra mode is assigned to a neighboring block adjacent to the current luma block if the neighboring block is coded in BDPCM (Block-based Delta Pulse Code Modulation) mode, where the predefined Intra mode is set to horizontal mode or vertical mode depending on prediction direction used by the BDPCM mode.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: April 9, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Man-Shu Chiang, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang, Shih-Ta Hsiang
  • Patent number: 11956469
    Abstract: Video processing methods and apparatuses implemented in a video encoding or decoding system with conditional secondary transform signaling. The video encoding system determines and applies a transform operation to residuals of a transform block to generate final transform coefficients, and adaptively signals a secondary transform index according to a position of a last significant coefficient in the transform block. A value of the secondary transform index is determined according to the transform operation.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: April 9, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Man-Shu Chiang, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen
  • Publication number: 20240113166
    Abstract: A method for fabricating semiconductor devices includes forming channel regions over a substrate. The channel regions, in parallel with one another, extend along a first lateral direction. Each channel region includes at least a respective pair of epitaxial structures. The method includes forming a gate structure over the channel regions, wherein the gate structure extends along a second lateral direction. The method includes removing, through a first etching process, a portion of the gate structure that was disposed over a first one of the channel regions. The method includes removing, through a second etching process, a portion of the first channel region. The second etching process includes one silicon etching process and one silicon oxide deposition process. The method includes removing, through a third etching process controlled based on a pulse signal, a portion of the substrate that was disposed below the removed portion of the first channel region.
    Type: Application
    Filed: February 15, 2023
    Publication date: April 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Ging Lin, Chun-Liang Lai, Yun-Chen Wu, Ya-Yi Tsai, Shu-Yuan Ku, Shun-Hui Yang
  • Publication number: 20240114810
    Abstract: A semiconductor structure includes: an etch-stop dielectric layer overlying a substrate and including a first opening therethrough; a silicon oxide plate overlying the etch-stop dielectric layer and including a second opening therethrough; a first conductive structure including a first electrode and extending through the second opening and the first opening; a memory film contacting a top surface of the first conductive structure and including a material that provides at least two resistive states having different electrical resistivity; and a second conductive structure including a second electrode and contacting a top surface of the memory film.
    Type: Application
    Filed: April 20, 2023
    Publication date: April 4, 2024
    Inventors: Fu-Ting Sung, Jhih-Bin Chen, Hung-Shu Huang, Hong Ming Liu, Hsia-Wei Chen, Yu-Wen Liao, Wen-Ting Chu
  • Patent number: 11948837
    Abstract: A method for making a semiconductor structure includes: providing a substrate with a contact feature thereon; forming a dielectric layer on the substrate; etching the dielectric layer to form an interconnect opening exposing the contact feature; forming a metal layer on the dielectric layer and outside of the contact feature; and forming a graphene conductive structure on the metal layer, the graphene conductive structure filling the interconnect opening, being electrically connected to the contact feature, and having at least one graphene layer that extends in a direction substantially perpendicular to the substrate.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Fu Yeh, Chin-Lung Chung, Shu-Wei Li, Yu-Chen Chan, Shin-Yi Yang, Ming-Han Lee
  • Patent number: 11944017
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes an insulation layer. A bottom electrode via is disposed in the insulation layer. The bottom electrode via includes a conductive portion and a capping layer over the conductive portion. A barrier layer surrounds the bottom electrode via. A magnetic tunneling junction (MTJ) is disposed over the bottom electrode via.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tai-Yen Peng, Yu-Shu Chen, Chien Chung Huang, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
  • Patent number: 11942348
    Abstract: An optical system may include a light source to provide a beam of light. The optical system may include a reflector to receive and redirect the beam of light. The optical system may include a light gate having an opening to permit the beam of light, from the reflector, to travel through the opening. The optical system may include a light sensor to receive a portion of the beam of light after the beam of light travels through the opening, and convert the portion of the beam of light to a signal. The optical system may include a processing device to determine whether a notch of a wafer is in an allowable position based on the signal.
    Type: Grant
    Filed: December 2, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-An Chuang, Kuang-Wei Hsueh, Shih-Huan Chen, Yung-Shu Kao
  • Patent number: 11943476
    Abstract: Video processing methods and apparatuses implemented in a video encoding or decoding system with conditional secondary transform signaling. The video encoding system determines and applies a transform operation to residuals of one or more transform blocks to generate final transform coefficients, and skip signaling a secondary transform index if a position of a last significant coefficient in each considered transform block is less than or equal to a predefined position; otherwise, the video encoding system signals a secondary transform index according to the transform operation.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: March 26, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Man-Shu Chiang, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen
  • Publication number: 20240094411
    Abstract: A global positioning system (GPS)-bias detection and reduction system including a GPS-bias model having GPS statistical data creating a database representing data collected from a vehicle group having thousands or multiple thousands of vehicles saved in a database. At least one newly collected vehicle GPS data point is compared to the GPS statistical data to reduce negative effects of GPS-bias and to update the vehicle GPS-bias correction based on a previous GPS-bias model. A selected road node and a segment of a roadway have a map matching performed using a nearest service from a collection location of the GPS statistical data. A GPS-bias is calculated using a look-up of the database. An estimated horizontal position error (EHPE) defining a quality indicator is applied to distinguish a good quality GPS statistical data from a poor quality GPS statistical data.
    Type: Application
    Filed: September 21, 2022
    Publication date: March 21, 2024
    Inventors: Gui Chen, Shu Chen, Bo Yu, Joon Hwang, Carl P. Darukhanavala, Vivek Vijaya Kumar
  • Publication number: 20240095293
    Abstract: Disclosed in embodiments of the present invention are a processing method and apparatus based on an interest tag, a device, and a storage medium. The method comprises: in a process of displaying an information flow in a preset application program, detecting that an interest tag display event is triggered; and displaying a first page, and dynamically switching and displaying, in the first page, different subsets in a preset interest tag set, wherein the number of interest tags in the subsets is more than one and is smaller than the total number of interest tags in the preset interest tag set.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Wenyang GAO, Shu CHEN, Zeyu LI
  • Publication number: 20240099150
    Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
  • Publication number: 20240085210
    Abstract: A method of creating a high-definition (HD) map of a roadway includes receiving a multi-layer probability density bitmap. The multi-layer probability density bitmap represents a plurality of lane lines of the roadway sensed by a plurality of sensors of a plurality of vehicles. The multi-layer probability density bitmap includes a plurality of points. The method further includes recursively conducting a hill climbing search using the multi-layer probability density bitmap to create a plurality of lines. In addition, the method includes creating the HD map of the roadway using the plurality of lines determined by the hill climbing search.
    Type: Application
    Filed: September 8, 2022
    Publication date: March 14, 2024
    Inventors: Bo Yu, Fan Bai, Gui Chen, Joon Hwang, Carl P. Darukhanavala, Vivek Vijaya Kumar, Shu Chen, Donald K. Grimm
  • Publication number: 20240086685
    Abstract: A method, apparatus, device and storage medium for recommending information. The method includes determining, based on a set of feature representations of a plurality of features associated with information recommendation, a first set of weights indicating importance of the plurality of features. The method also includes determining a second set of weights based on the set of feature representations and the first set of weights. The method further includes recommending the information to a user based on the set of feature representations, the first set of weights and the second set of weights. The importance of respective features associated with the information recommendation can be accurately determined through this method, which further improves the effectiveness of information recommendation and improves the user experience.
    Type: Application
    Filed: September 8, 2023
    Publication date: March 14, 2024
    Inventors: Xiaosong ZHOU, Qingliang CAI, Shu CHEN, Zhe WANG, Haiqian HE
  • Publication number: 20240088095
    Abstract: A method for forming a chip package structure. The method includes bonding first connectors over a front surface of a semiconductor wafer. The method also includes dicing the semiconductor wafer from a rear surface of the semiconductor wafer to form semiconductor dies and mounting first and second semiconductor dies in the semiconductor dies over a top surface of the interposer substrate. The method further forming an encapsulating layer over the top surface of the interposer substrate to cover the first semiconductor die and the second semiconductor die. A first sidewall of the first semiconductor die faces a second sidewall of the second semiconductor die, and upper portions of the first sidewall and the second sidewall have a tapered contour, to define a top die-to-die distance and a bottom die-to-die distance that is less than the top die-to-die distance.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 14, 2024
    Inventors: Chin-Hua WANG, Shin-Puu JENG, Po-Yao LIN, Po-Chen LAI, Shu-Shen YEH, Ming-Chih YEW, Yu-Sheng LIN
  • Publication number: 20240088042
    Abstract: A semiconductor structure includes a dielectric layer over a substrate, a via conductor over the substrate and in the dielectric layer, and a first graphene layer disposed over the via conductor. In some embodiments, a top surface of the via conductor and a top surface of the dielectric layer are level. In some embodiments, the first graphene layer overlaps the via conductor from a top view. In some embodiments, the semiconductor structure further includes a second graphene layer under the via conductor and a third graphene layer between the dielectric layer and the via conductor. In some embodiments, the second graphene layer is between the substrate and the via conductor.
    Type: Application
    Filed: January 11, 2023
    Publication date: March 14, 2024
    Inventors: SHU-WEI LI, HAN-TANG HUNG, YU-CHEN CHAN, CHIEN-HSIN HO, SHIN-YI YANG, MING-HAN LEE, SHAU-LIN SHUE
  • Patent number: 11929561
    Abstract: An antenna module includes a first antenna radiator including a feeding terminal, a second antenna radiator, a first ground radiator, a second ground radiator and a capacitive element. The second antenna radiator is disposed on one side of the first antenna radiator, and a first gap is formed between a main portion of the second antenna radiator and the first antenna radiator. The first ground radiator is disposed on another side of the first antenna radiator, and a second gap is formed between the first antenna radiator and the first antenna radiator. The second ground radiator is disposed between the second antenna radiator and the first ground radiator, and a third gap is formed between the second ground radiator and a first branch of the second antenna radiator. The capacitive element is disposed on the third gap and connects the second antenna radiator and the second ground radiator.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: March 12, 2024
    Assignee: PEGATRON CORPORATION
    Inventors: I-Shu Lee, Chih-Hung Cho, Hau Yuen Tan, Chien-Yi Wu, Po-Sheng Chen, Chao-Hsu Wu, Yi Chen, Hung-Ming Yu, Chih-Chien Hsieh
  • Patent number: 11929293
    Abstract: A semiconductor package includes a substrate, a package structure, and a lid structure. The package structure is disposed on the substrate. The lid structure is disposed over substrate, wherein the lid structure includes a main body covering and surrounding the package structure and a plurality of rib portions protruded from the main body and extended toward the package structure.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Shu Lin, Wensen Hung, Tsung-Yu Chen
  • Publication number: 20240080490
    Abstract: A video codec receives data for a block of pixels to be encoded or decoded as a current block of a current picture of a video. The video codec signals or parses a first syntax element for a first coding mode in a particular set of two or more coding modes. Each of coding mode of the particular set of coding modes modifies a merge candidate or an inter-prediction that is generated based on the merge candidate. The video codec enables the first coding mode and disables one or more other coding modes in the particular set of coding modes. The disabled one or more coding modes in the particular set of coding modes are disabled without parsing syntax elements for the disabled coding modes. The video codec encodes or decodes the current block by using the enabled first coding mode and bypassing the disabled coding modes.
    Type: Application
    Filed: November 10, 2023
    Publication date: March 7, 2024
    Applicant: HFI Innovation Inc.
    Inventors: Man-Shu Chiang, Chih-Wei Hsu, Ching-Yeh Chen
  • Patent number: 11921434
    Abstract: An apparatus includes a vacuum chamber, a reflective optical element arranged in the vacuum chamber and configured to reflect an extreme ultra-violet (EUV) light, and a cleaning module positioned in the vacuum chamber. the cleaning module is operable to provide a mitigation gas flowing towards the reflective optical element and provide a hydrogen-containing gas flowing towards the reflective optical element. The mitigation gas mitigates, by chemical reaction, contamination of the reflective optical element.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Hao Chang, Norman Chen, Jeng-Horng Chen, Kuo-Chang Kau, Ming-Chin Chien, Shang-Chieh Chien, Anthony Yen, Kevin Huang