Abstract: A method of fabricating a semiconductor device includes forming a gate structure, a first edge structure and a second edge structure on a semiconductor strip. The method further includes forming a first source/drain feature between the gate structure and the first edge structure. The method further includes forming a second source/drain feature between the gate structure and the second edge structure, wherein a distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature. The method further includes implanting a buried channel in the semiconductor strip, wherein the buried channel is entirely below a top-most surface of the semiconductor strip, a maximum depth of the buried channel is less than a maximum depth of the first source/drain feature, and a dopant concentration of the buried channel is highest under the gate structure.

Abstract: A method for processing noise interference in a serial advanced technology attachment (SATA) interface. In the method, when a receiver does not receive a SOF primitive (start of frame primitive) but does receive an EOF primitive (end of frame primitive) or WTRM primitive (wait for frame termination primitive), the receiver outputs a R_ERR primitive (reception error primitive) to enable a transmitter to resend original data and thus to eliminate the interference. In addition, if the transmitter detects an error during the data transmission, a HOLD primitive (hold data transmission primitive) will be issued to temporarily stop the data transmission.

Abstract: A method for processing noise interference in a serial AT Attachment (SATA) interface. The method includes the steps of detecting whether there is an error in CRC (Cyclic Redundancy Check) checksum or whether an R_ERR primitive (reception error primitive) is received, detecting whether a FIS (Frame Information Structure) is a data type if there is any error and returning back to error state detecting step if there is no any error, detecting whether the FIS is a ATAPI packet command CDB (Command Descriptor Block) when the FIS is the data format, and writing a special tag to the CDB and returning back to the error detecting step.

Abstract: A method for processing noise interference in a serial AT Attachment (SATA) interface. The method includes the steps of detecting whether there is an error in CRC (Cyclic Redundancy Check) checksum or whether an R_ERR primitive (reception error primitive) is received, detecting whether a FIS (Frame Information Structure) is a data type if there is any error and returning back to error state detecting step if there is no any error, detecting whether the FIS is a ATAPI packet command CDB (Command Descriptor Block) when the FIS is the data format, and writing a special tag to the CDB and returning back to the error detecting step.

Abstract: A defect management method applied in an optical disc drive for managing defect information of an optical disc is disclosed. The optical disc drive saves a plurality of defect tables comprising at least a first defect table and a second defect table. The first defect table records a plurality of first defect entries and the second defect table records a plurality of second defect entries. The method includes appending an adaptive defect entry comprising a new defect information corresponding to a new defect into a new defect table, a data structure of the adaptive defect entry conforming to a data structure of at least one of the defect entries recorded in the defect tables; and merging the adaptive defect entries into one of the defect tables saved in the optical disc drive when a condition is met.

Abstract: A method and circuit for reducing SATA (Serial Advanced Technology Attachment) transmission data errors by adjusting the period of sending two consecutive ALIGN Primitives. The method reads a counting value of an 8b/10b coding error counter at a predetermined period and adjusts the period of sending two consecutive ALIGN Primitives according to the counting value. Because the system dynamically adjusts the period of sending two consecutive ALIGN Primitives according to the channel condition, the SATA transmission data errors can be reduced.

Abstract: A method for processing noise interference in a serial advanced technology attachment (SATA) interface. In the method, when a receiver does not receive a SOF primitive (start of frame primitive) but does receive an EOF primitive (end of frame primitive) or WTRM primitive (wait for frame termination primitive), the receiver outputs a R_ERR primitive (reception error primitive) to enable a transmitter to resend original data and thus to eliminate the interference. In addition, if the transmitter detects an error during the data transmission, a HOLD primitive (hold data transmission primitive) will be issued to temporarily stop the data transmission.

Abstract: A method for processing noise interference in a serial AT Attachment (SATA) interface. In the method, when a receiver does not receive a SOF primitive (start of frame primitive) but does receive an EOF primitive (end of frame primitive) or WTRM primitive (wait for frame termination primitive), the receiver outputs a R_ERR primitive (reception error primitive) to enable a transmitter to resend original data and thus to eliminate the interference. In addition, if the transmitter detects an error during the data transmission, a HOLD primitive (hold data transmission primitive) will be issued to temporarily stop the data transmission.

Abstract: An optical storage device that includes a memory and a controller. The memory includes a command queue to store advanced technology attachment (ATA) commands sent by a host device. The controller executes the commands, in which at least a subset of the commands are executed in a sequence that is different from a sequence in which the commands are sent by the host device.

Abstract: An optical storage device that includes a memory and a controller. The memory includes a command queue to store advanced technology attachment (ATA) commands sent by a host device. The controller executes the commands, in which at least a subset of the commands are executed in a sequence that is different from a sequence in which the commands are sent by the host device.

Abstract: A method and circuit for reducing SATA (Serial Advanced Technology Attachment) transmission data errors by adjusting the period of sending two consecutive ALIGN Primitives. The method reads a counting value of an 8b/10b coding error counter at a predetermined period and adjusts the period of sending two consecutive ALIGN Primitives according to the counting value. Because the system dynamically adjusts the period of sending two consecutive ALIGN Primitives according to the channel condition, the SATA transmission data errors can be reduced.

Abstract: A method and circuit for reducing SATA (Serial Advanced Technology Attachment) transmission data errors by adjusting the period of sending two consecutive ALIGN Primitives. The method reads a counting value of an 8b/10b coding error counter at a predetermined period and adjusts the period of sending two consecutive ALIGN Primitives according to the counting value. Because the system dynamically adjusts the period of sending two consecutive ALIGN Primitives according to the channel condition, the SATA transmission data errors can be reduced.

Abstract: A method for processing noise interference in a serial AT Attachment (SATA) interface. The method includes the steps of detecting whether there is an error in CRC (Cyclic Redundancy Check) checksum or whether an R_ERR primitive (reception error primitive) is received, detecting whether a FIS (Frame Information Structure) is a data type if there is any error and returning back to error state detecting step if there is no any error, detecting whether the FIS is a ATAPI packet command CDB (Command Descriptor Block) when the FIS is the data format, and writing a special tag to the CDB and returning back to the error detecting step.

Abstract: A system includes a first device; an Integrated Drive Electronics (IDE) bus; and a data storage device having a first task file register, the data storage device being coupled to the first device via the IDE bus for storing data within the data storage device as received from the first device via the IDE bus, or for passing the data stored within the data storage device to the first device via the IDE bus according to commands passed from the first device via the IDE bus. The data storage device is further for controlling predetermined operations of the first device by storing different values within the first task file register, and the first device is for reading the first task file register of the data storage device via the IDE bus and performing the predetermined operations according to the different values.

Abstract: A method for processing noise interference in a serial AT Attachment (SATA) interface. The method includes the steps of detecting whether there is an error in CRC (Cyclic Redundancy Check) checksum or whether an R_ERR primitive (reception error primitive) is received, detecting whether a FIS (Frame Information Structure) is a data type if there is any error and returning back to error state detecting step if there is no any error, detecting whether the FIS is a ATAPI packet command CDB (Command Descriptor Block) when the FIS is the data format, and writing a special tag to the CDB and returning back to the error detecting step.

Abstract: A method for processing noise interference in a serial AT Attachment (SATA) interface. The method includes the steps of detecting whether there is an error in CRC (Cyclic Redundancy Check) checksum or whether an R_ERR primitive (reception error primitive) is received, detecting whether a FIS (Frame Information Structure) is a data type if there is any error and returning back to error state detecting step if there is no any error, detecting whether the FIS is a ATAPI packet command CDB (Command Descriptor Block) when the FIS is the data format, and writing a special tag to the CDB and returning back to the error detecting step.

Abstract: An optical storage device that includes a memory and a controller. The memory includes a command queue to store advanced technology attachment (ATA) commands sent by a host device. The controller executes the commands, in which at least a subset of the commands are executed in a sequence that is different from a sequence in which the commands are sent by the host device.

Abstract: A system includes a first device; an Integrated Drive Electronics (IDE) bus; and a data storage device having a first task file register, the data storage device being coupled to the first device via the IDE bus for storing data within the data storage device as received from the first device via the IDE bus, or for passing the data stored within the data storage device to the first device via the IDE bus according to commands passed from the first device via the IDE bus. The data storage device is further for controlling predetermined operations of the first device by storing different values within the first task file register, and the first device is for reading the first task file register of the data storage device via the IDE bus and performing the predetermined operations according to the different values.

Abstract: A defect management method applied in an optical disc drive for managing defect information of an optical disc is disclosed. The optical disc drive saves a plurality of defect tables comprising at least a first defect table and a second defect table. The first defect table records a plurality of first defect entries and the second defect table records a plurality of second defect entries. The method includes appending an adaptive defect entry comprising a new defect information corresponding to a new defect into a new defect table, a data structure of the adaptive defect entry conforming to a data structure of at least one of the defect entries recorded in the defect tables; and merging the adaptive defect entries into one of the defect tables saved in the optical disc drive when a condition is met.

Abstract: A bridge system having at least one bridge chip to control the operations of the bridge. Each bridge chip uniquely connects to a bus interface allowing communications between a host system and the bridge chip when that bus interface is to be utilized. Each bridge chip also connects to another bus interface connecting the bridge with a device. Each bridge chip includes an activation circuit that automatically disables that bridge chip after a power-on or a hardware reset occurs. When the activation circuit receives a protocol initialization signal, the activation circuit causes only the associated bridge chip to become enabled. Once enabled, the bridge chip drives all of the pins in the bus interface connecting the bridge with the device and remains in control of that bus interface until a power-off, a hardware reset occurs, or the bridge chip has been physically disconnected from the host.