Abstract: A device includes a gate stack having a top portion, and a stacked structure underlying the top portion of the gate stack. The stacked structure includes a plurality of semiconductor nanostructures, with upper nanostructures in the plurality of semiconductor nanostructures overlapping respective lower nanostructures. The stacked structure further includes a plurality of gate structures, each including a lower portion of the gate stack. Each of the plurality of gate structures is between two of the plurality of semiconductor nanostructures. A dielectric layer extends on a top surface and a sidewall of the stacked structure. The dielectric layer includes a lower sub layer comprising a first dielectric material, and an upper sub layer over the lower sub layer and formed of a second dielectric material different from the first dielectric material. A gate spacer is on the dielectric layer. A source/drain region is aside of the gate stack.

Abstract: In an embodiment, a structure includes: a nano-structure; an epitaxial source/drain region adjacent the nano-structure; a gate dielectric wrapped around the nano-structure; a gate electrode over the gate dielectric, the gate electrode having an upper portion and a lower portion, a first width of the upper portion increasing continually in a first direction extending away from a top surface of the nano-structure, a second width of the lower portion being constant along the first direction; and a gate spacer between the gate dielectric and the epitaxial source/drain region.

Abstract: A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.

Abstract: A device includes a first channel layer, a second channel layer, a gate structure, a source/drain epitaxial structure, and a source/drain contact. The first channel layer and the second channel layer are arranged above the first channel layer in a spaced apart manner over a substrate. The gate structure surrounds the first and second channel layers. The source/drain epitaxial structure is connected to the first and second channel layers. The source/drain contact is connected to the source/drain epitaxial structure. The second channel layer is closer to the source/drain contact than the first channel layer is to the source/drain contact, and the first channel layer is thicker than the second channel layer.

Abstract: A method for predicting clinical severity of a neurological disorder includes steps of: a) identifying, according to a magnetic resonance imaging (MRI) image of a brain, brain image regions each of which contains a respective portion of diffusion index values of a diffusion index, which results from image processing performed on the MRI image; b) for one of the brain image regions, calculating a characteristic parameter based on the respective portion of the diffusion index values; and c) calculating a severity score that represents the clinical severity of the neurological disorder of the brain based on the characteristic parameter of the one of the brain image regions via a prediction model associated with the neurological disorder.

Abstract: In a method of manufacturing a semiconductor device, a field effect transistor (FET) having a metal gate structure, a source and a drain over a substrate is formed. A first frontside contact disposed between dummy metal gate structures is formed over an isolation insulating layer. A frontside wiring layer is formed over the first frontside contact. A part of the substrate is removed from a backside of the substrate so that a bottom of the isolation insulating layer is exposed. A first opening is formed in the isolation insulating layer from the bottom of the isolation insulating layer to expose a bottom of the first frontside contact. A first backside contact is formed by filling the first opening with a conductive material to connect the first frontside contact.

Abstract: A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.

Abstract: Gate profile tuning techniques are disclosed herein. An exemplary gate profile tuning method includes forming a gate structure over a channel layer. The gate structure includes a dummy gate and gate spacers disposed along sidewalls of the dummy gate. The method further includes partially removing the dummy gate to form a gate opening that defines a gate profile. The gate profile is then modified by treating portions of the gate spacers (for example, by oxygen plasma treatment) and removing the treated portions of the gate spacers (for example, by oxide removal). After removing a remainder of the dummy gate to expose the channel layer, a gate stack of the gate structure is formed in the gate opening. The gate stack has a funnel-shaped profile. In some embodiments, a width of the gate stack above the channel layer is greater than a width of the gate stack below the channel layer.

Abstract: A device includes a first channel layer, a second channel layer, a gate structure, a source/drain epitaxial structure, and a source/drain contact. The first channel layer and the second channel layer are arranged above the first channel layer in a spaced apart manner over a substrate. The gate structure surrounds the first and second channel layers. The source/drain epitaxial structure is connected to the first and second channel layers. The source/drain contact is connected to the source/drain epitaxial structure. The second channel layer is closer to the source/drain contact than the first channel layer is to the source/drain contact, and the first channel layer is thicker than the second channel layer.

Abstract: A device includes a semiconductor nanostructure, and an oxide layer, which includes horizontal portions on a top surface and a bottom surface of the semiconductor nanostructure, vertical portions on sidewalls of the semiconductor nanostructure, and corner portions on corners of the semiconductor nanostructure. The horizontal portions have a first thickness. The vertical portions have a second thickness. The corner portions have a third thickness. Both of the second thickness and the third thickness are greater than the first thickness. A high-k dielectric layer surrounds the oxide layer. A gate electrode surrounds the high-k dielectric layer.

Abstract: A device includes a semiconductor nanostructure, and an oxide layer, which includes horizontal portions on a top surface and a bottom surface of the semiconductor nanostructure, vertical portions on sidewalls of the semiconductor nanostructure, and corner portions on corners of the semiconductor nanostructure. The horizontal portions have a first thickness. The vertical portions have a second thickness. The corner portions have a third thickness. Both of the second thickness and the third thickness are greater than the first thickness. A high-k dielectric layer surrounds the oxide layer. A gate electrode surrounds the high-k dielectric layer.

Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, an isolation insulating layer is formed such that an upper portion of the fin structure protrudes from the isolation insulating layer, a gate dielectric layer is formed by a deposition process, a nitridation operation is performed on the gate dielectric layer, and a gate electrode layer is formed over the gate dielectric layer. The gate dielectric layer as formed includes silicon oxide, and the nitridation operation comprises a plasma nitridation operation using a N2 gas and a NH3 gas.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method for manufacturing the semiconductor structure includes forming a fin structure protruding from a substrate, and the fin structure includes first semiconductor material layers and second semiconductor material layers alternately stacked. The method also includes forming a dummy gate structure across the fin structure and forming a gate spacer on a sidewall of the dummy gate structure. The method also includes partially oxidizing the gate spacer to form an oxide layer and removing the oxide layer to form a modified gate spacer. The method also includes removing the first semiconductor material layers to form gaps and forming a gate structure in the gaps to wrap around the second semiconductor material layers and over the second semiconductor material layers to cover the modified gate spacer.

Abstract: A method of forming a nanostructure field-effect transistor (nano-FET) device includes: forming a fin structure that includes a fin and alternating layers of a first semiconductor material and a second semiconductor material overlying the fin; forming a dummy gate structure over the fin structure; forming source/drain regions over the fin structure on opposing sides of the dummy gate structure; removing the dummy gate structure to expose the first and second semiconductor materials under the dummy gate structure; selectively removing the exposed first semiconductor material, where after the selectively removing, the exposed second semiconductor material remains to form nanostructures, where different surfaces of the nanostructures have different atomic densities of the second semiconductor material; forming a gate dielectric layer around the nanostructures, thicknesses of the gate dielectric layer on the different surfaces of the nanostructures being formed substantially the same; and forming a gate electrode

Abstract: A method includes forming a dummy gate oxide on a wafer, and the dummy gate oxide is formed on a sidewall and a top surface of a protruding semiconductor fin in the wafer. The formation of the dummy gate oxide may include a Plasma Enhanced Chemical Vapor Deposition (PECVD) process in a deposition chamber, and the PECVD process includes applying a Radio Frequency (RF) power to a conductive plate below the wafer. The method further includes forming a dummy gate electrode over the dummy gate oxide, removing the dummy gate electrode and the dummy gate oxide to form a trench between opposing gate spacers, and forming a replacement gate in the trench.

Abstract: A method for forming a semiconductor device structure includes forming alternating first semiconductor layers and second semiconductor layers stacked over a substrate. The method also includes etching the first semiconductor layers and the second semiconductor layers to form a fin structure. The method also includes oxidizing the first semiconductor layers to form first oxidized portions of the first semiconductor layers and oxidizing the second semiconductor layers to form second oxidized portions of the second semiconductor layers. The method also includes removing the oxides over the sidewalls of the second semiconductor layers. After removing the second oxidized portions, an upper layer of the second semiconductor layers is narrower than a lower layer of the second semiconductor layers. The method also includes removing the first semiconductor layers to form a gate opening between the second semiconductor layers. The method also includes forming a gate structure in the gate opening.

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer.

Abstract: In an embodiment, a structure includes: a nano-structure; an epitaxial source/drain region adjacent the nano-structure; a gate dielectric wrapped around the nano-structure; a gate electrode over the gate dielectric, the gate electrode having an upper portion and a lower portion, a first width of the upper portion increasing continually in a first direction extending away from a top surface of the nano-structure, a second width of the lower portion being constant along the first direction; and a gate spacer between the gate dielectric and the epitaxial source/drain region.

Abstract: A device includes a first channel layer, a second channel layer, a gate structure, a source/drain epitaxial structure, and a source/drain contact. The first channel layer and the second channel layer are arranged above the first channel layer in a spaced apart manner over a substrate. The gate structure surrounds the first and second channel layers. The source/drain epitaxial structure is connected to the first and second channel layers. The source/drain contact is connected to the source/drain epitaxial structure. The second channel layer is closer to the source/drain contact than the first channel layer is to the source/drain contact, and the first channel layer is thicker than the second channel layer.