Abstract: A semiconductor package structure includes an interposer substrate formed over a package substrate. The structure also includes a die disposed over the interposer substrate. The structure also includes a first heat spreader disposed over the package substrate. The structure also includes a second heat spreader disposed over the die and connected to the first heat spreader. The coefficient of thermal expansion (CTE) of the first heat spreader and the coefficient of thermal expansion of the second heat spreader are different.

Abstract: A semiconductor package structure includes an interposer substrate formed over a package substrate. The structure also includes a die disposed over the interposer substrate. The structure also includes a first heat spreader disposed over the package substrate. The structure also includes a second heat spreader disposed over the die and connected to the first heat spreader. The coefficient of thermal expansion (CTE) of the first heat spreader and the coefficient of thermal expansion of the second heat spreader are different.

Abstract: Semiconductor devices and methods of manufacture which utilize lids in order to constrain thermal expansion during annealing are presented. In some embodiments lids are placed and attached on encapsulant and, in some embodiments, over first semiconductor dies. As such, when heat is applied, and the encapsulant attempts to expand, the lid will work to constrain the expansion, reducing the amount of stress that would otherwise accumulate within the encapsulant.

Abstract: A multi-chip device includes a first material within a substrate. The first material has a first coefficient of thermal expansion different than a second coefficient of thermal expansion of the substrate. A first chip overlies a first portion of the first material and a first portion of the substrate. A second chip overlies a second portion of the first material and a second portion of the substrate. The first material is between the first portion of the substrate and the second portion of the substrate.

Abstract: Some embodiments relate to a semiconductor structure. The semiconductor structure includes a first substrate including a first plurality of conductive pads that are laterally spaced apart from one another on the first substrate. A first plurality of conductive bumps are disposed on the first plurality of conductive pads, respectively. A multi-tiered solder-resist structure is disposed on the first substrate and arranged between the first plurality of conductive pads. The multi-tiered solder-resist structure has different widths at a different heights over the first substrate and contacts sidewalls of the first plurality of conductive bumps to separate the first plurality of conductive bumps from one another.

Abstract: A chip package includes a substrate, a semiconductor chip, and a thermal conductive structure. The chip package includes a first and a second support structures below the thermal conductive structure. The first and the second support structures connect the substrate and corners of the thermal conductive structure. The thermal conductive structure has a side edge connecting the first and the second support structures. The first and the second support structures and the side edge together define of an opening exposing a space surrounding the semiconductor chip. The first and the second support structures are disposed along a side of the substrate. The first support structure is laterally separated from the side of the substrate by a first lateral distance. The side edge of the thermal conductive structure is laterally separated from the side of the substrate by a second lateral distance different than the first lateral distance.

Abstract: A semiconductor package is provided, which includes a first chip disposed over a first package substrate, a molding compound surrounding the first chip, a first thermal interface material disposed over the first chip and the molding compound, a heat spreader disposed over the thermal interface material, and a second thermal interface material disposed over the heat spreader. The first thermal interface material and the second thermal interface material have an identical width.

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.

Abstract: A method for forming a chip package structure. The method includes bonding first connectors over a front surface of a semiconductor wafer. The method also includes dicing the semiconductor wafer from a rear surface of the semiconductor wafer to form semiconductor dies and mounting first and second semiconductor dies in the semiconductor dies over a top surface of the interposer substrate. The method further forming an encapsulating layer over the top surface of the interposer substrate to cover the first semiconductor die and the second semiconductor die. A first sidewall of the first semiconductor die faces a second sidewall of the second semiconductor die, and upper portions of the first sidewall and the second sidewall have a tapered contour, to define a top die-to-die distance and a bottom die-to-die distance that is less than the top die-to-die distance.

Abstract: An semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill layer and an encapsulant. The first semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface and a first side surface connecting with the first bottom surface and the first top surface, the first side surface comprises a first sub-surface and a second sub-surface connected with each other, the first sub-surface is connected with the first bottom surface, and a first obtuse angle is between the first sub-surface and the second sub-surface.

Abstract: A semiconductor package provided herein includes a wiring substrate, a semiconductor component, conductor terminals, a bottom stiffener and a top stiffener. The wiring substrate has a first surface and a second surface opposite to the first surface. The semiconductor component is disposed on the first surface of the wiring substrate. The conductor terminals are disposed on the second surface of the wiring substrate and electrically connected to the semiconductor component through the wiring substrate. The bottom stiffener is disposed on the second surface of the wiring substrate and positioned between the conductor terminals. The top stiffener is disposed on the first surface of the wiring substrate. The top stiffener is laterally spaced further away from the semiconductor component than the bottom stiffener.

Abstract: The present invention discloses an organic compound represented by the following formula (1) and an organic electroluminescence device using the organic compound as the phosphorescent host material, the fluorescent host material, or the fluorescent dopant material. The organic compound may increase a current efficiency or half-life of the organic electroluminescence device.

Abstract: An organic compound which can be used as the phosphorescent host material, the fluorescent host material, or the fluorescent dopant material of the light emitting layer, and/or the electron transporting material of the organic electroluminescence device is disclosed. The organic electroluminescence device employing the organic compound can lower driving voltage, prolong half-lifetime, and increase current efficiency.

Abstract: An organic compound is described. An organic electroluminescence device comprises the organic compound as a host or a hole blocking layer. The organic compound of the following formula may lower a driving voltage or increases a current efficiency or a half-life of the organic electroluminescence device. The same definition as described in the present invention.

Abstract: The present invention discloses an organic compound represented by the following formula (1) and an organic electroluminescence device using the organic compound as the phosphorescent host material, the fluorescent host material, or the fluorescent dopant material. The organic compound may increase a current efficiency or half-life of the organic electroluminescence device. The same definition as described in the present invention.

Abstract: An organic compound which can be used as the phosphorescent host material, the fluorescent host material, or the fluorescent dopant material of the light emitting layer, and/or the electron transporting material of the organic electroluminescence device is disclosed. The organic electroluminescence device employing the organic compound can lower driving voltage, prolong half-lifetime, and increase current efficiency.

Abstract: An organic compound which can be used as the phosphorescent host material, the fluorescent host material, or the fluorescent dopant material of the light emitting layer, and/or the electron transporting material of the organic electroluminescence device is disclosed. The organic electroluminescence device employing the organic compound can lower driving voltage, prolong half-lifetime, and increase luminance and current efficiency.

Abstract: The present invention discloses an indenotriphenylene phosphine oxide derivative and an organic electroluminescence device employing the derivative as the phosphorescent host material in the light emitting layer, and/or the hole blocking material and/or the electron transporting material in the organic EL device, which thereby exhibits improved performance.

Abstract: The present invention discloses an indenotriphenylene phosphine oxide derivative and an organic electroluminescence device employing the derivative as the phosphorescent host material in the light emitting layer, and/or the hole blocking material and/or the electron transporting material in the organic EL device, which thereby exhibits improved performance.

Abstract: A lamp includes a frame, a light guide plate, a light source and a reflecting structure. The light guide plate is disposed on the frame and includes a light-incident surface, a first light-emitting surface and a second light-emitting surface. The second light-emitting surface is opposite to the first light-emitting surface, in which the light-incident surface connects the first light-emitting surface and the second light-emitting surface. The light source is adjacent to the light-incident surface and the light source is disposed in the frame. The reflecting structure is adjacent to the first light-emitting surface and includes at least two transparent sheets. The two transparent sheets are separated by an air gap, such that at least one light beam emitted from the first light-emitting surface is reflected back to the light guide plate and is emitted out from the second light-emitting surface.