Abstract: The present invention provides BRACE inhibitors of Formula (I): methods for their use, and intermediates and methods for their preparation.

Abstract: The present invention relates to a hydrophilic surface structure of the non-hydrophilic substrate and the manufacturing method for using the same. The hydrophilic substrate surface structure is fabricated by forming an amphiphilic polymer layer, a cross-linked stacking layer, and a hydrophilic layer in sequence on the surface of a non-hydrophilic substrate. For example, the hydrophobic surface of poly(dimethylsiloxane) (PDMS) can be made from hydrophobic to hydrophilic and the hydrophilicity can be retained for a long period of time and resist protein adsorption. The hydrophilic thin films give long term stability to the PDMS surface by resisting hydrophobicity recovery, which is the major problem with PDMS. The disclosed method can further be used in the immobilization of protein and other molecules. This method can also be used for modifying other substrates which suffer problems of surface instability.

Abstract: An integrative microdialysis and chip-based electrophoresis system and analytical method using the same are disclosed. The system combines the microdialysis probe sampling technique and continuous pressure flow feeding coupled with chip-based electrophoresis analysis. It is capable of performing online sampling as well as rapid and continuous monitoring and analysis of biological samples. The system offers the advantages of real-time on-chip dye labeling, simple apparatus setup and easy operation.

Abstract: This invention relates to a layout structure for providing stable power supply to a four-layer motherboard and a main bridge chip substrate. In the invention, on the top signal layer and power path of the bottom solder layer for layout of the main bridge chip and on the power ring, the decoupling capacitors are connected in between the ground bonding pads/solder balls and the power bonding pads/solder balls of the power paths and power rings, so as to provide a stable power supply for the operation of the main bridge chip. In this invention, the ground bonding pad/solder ball connected with each power bonding pad/solder ball can be the closest ground bonding pad/solder ball to the power bonding pad/solder ball. In addition, in the embodiment of the main bridge chip substrate, decoupling capacitors can be disposed at four corners of the power ring or underneath the bonding wires, or can be packaged inside the molding compound.

Abstract: This invention relates to a layout structure for providing stable power supply to a four-layer motherboard and a main bridge chip substrate. In the invention, on the top signal layer and power path of the bottom solder layer for layout of the main bridge chip and on the power ring, the decoupling capacitors are connected in between the ground bonding pads/solder balls and the power bonding pads/solder balls of the power paths and power rings, so as to provide a stable power supply for the operation of the main bridge chip. In this invention, the ground bonding pad/solder ball connected with each power bonding pad/solder ball can be the closest ground bonding pad/solder ball to the power bonding pad/solder ball. In addition, in the embodiment of the main bridge chip substrate, decoupling capacitors can be disposed at four corners of the power ring or underneath the bonding wires, or can be packaged inside the molding compound.

Abstract: The present invention relates to a sample analysis system with chip-based electrophoresis device, particularly, the chip electrophoresis is connected to the dynamic flow-based auto-sampling device to introduce the sample into the chip-based electrophoresis device. By utilizing the derivatization biochemistry method to have a surface modification on the sample loading channel, it prevents the sample from being adhered to the wall of the sample loading channel, and hence increases the sample loading rate, reduces cross-contamination of samples and performs specific bio-reaction by using the immobilization of matter including antigen, antibody, protein, or enzyme. This invention makes use of the continuous split flow and electric voltage control to work with the detecting unit, signal collecting unit, and signal processing unit so that the sample undergoes a timely, fast, continuous analysis without having interference from the sample of other time.

Abstract: A layout structure of a central processing unit (CPU) that supports two different package techniques, comprising a motherboard that comprises the layout structure and a layout method. The layout structure of the preferred embodiment according to the present invention from up to down sequentially places a top signal layer, a grounded layer, a power layer having a grounded potential, and a bottom solder layer in the area where the signals of the CPU are coupled to the signals of the control chip, so that the signals that are placed on the bottom solder layer can refer to a grounded potential area of the power layer. Therefore, part of signals of the CPU that are coupled to the control chip can be placed on the bottom solder layer.

Abstract: A chipset to support multiple CPU's and a layout method thereof. Those independent signal lines for delivering high frequency clock signals of the chipset are isolated from using by other signals without being multiplexed. Trace length of the independent signal line is shorter than that of the others. The spaces between the independent signal line and others are also larger than that between other signal lines. Signal transmission quality is significantly upgraded because the high frequency clock signal is not multiplexed and isolated from others.

Abstract: A parent-children interactive intelligent management system for managing computer use authorization, time and operating system functions of users includes a computer device, a reading device and a memory device. When the memory device is inserted into the reading device, the computer device can process data management for data in the memory device and settings. When a child inserts the memory card into the reading device, the child can only use the operating system according to the set conditions in the memory card. Thus computer use time of the child may be restricted to prevent the child from accessing undesirable Web sites. The parent can leave messages and inquire the child about computer use status to enhance the interactive relationship between the parent and the child.

Abstract: The present invention is a placement that is utilized in a 4 layers motherboard and a main bridge chip substrate. The layout adds a placement of the power rings and the power paths on the top signal layer and the bottom solder layer of the main bridge chip on the motherboard, the second layer and the third layer are planned as grounded layers, so that all signals on the top signal layer and the bottom solder layer on the motherboard can easily refer to the grounded layer. The layout of the power ring and the power path on the top signal layer on the motherboard is symmetrical to the layout of the power ring and the power path on the bottom solder layer on the motherboard, and all power paths couple to the corresponding power rings. The power bonding pads/solder balls are arranged on the area where the power rings and the power paths pass through, and the moderate quantity of the grounded bonding pads are arranged on the both sides of the power paths.

Abstract: A layout structure of a central processing unit (CPU) that supports two different package techniques, comprising a motherboard that comprises the layout structure and a layout method. The layout structure of the preferred embodiment according to the present invention from up to down sequentially places a top signal layer, a grounded layer, a power layer having a grounded potential, and a bottom solder layer in the area where the signals of the CPU are coupled to the signals of the control chip, so that the signals that are placed on the bottom solder layer can refer to a grounded potential area of the power layer. Therefore, part of signals of the CPU that are coupled to the control chip can be placed on the bottom solder layer.

Abstract: The present invention provides an integrated microfluidic electrospray chip system and analytical method thereof, characterized in which the proteinase reaction, solid-phase extraction mechanism, electrophoresis and mass spectrometry are integrated into one system. This system allows continuous, fast and on-line detection and identification of a sample, where the sample is firstly hydrolyzed and desalted, and then introduced into the microfluidic electrospray chip to undergo electrophoresis. Finally, the separated sample is introduced into a mass spectrometer by means of electrospray for continuous detection and identification. This system applies mainly in the identification of biochemical substances, such as proteins.

Abstract: A layout structure of a central processing unit (CPU) that supports two different package techniques, having a motherboard that comprising the layout structure and a layout method. The layout structure of the preferred embodiment according to the present invention from up to down sequentially placed a top signal layer, a grounded layer, a power layer having an operating potential area and a grounded potential area, and a bottom solder layer in the area where the signals of the CPU are coupled to the signals of the control chip, so that the signals that are placed on the bottom solder layer can refer to a grounded potential area of the power layer.

Abstract: A method for modification of glass-based microchannels, which uses liquid organic-based solution containing siloxane for the modification of microchannels on the glass substrate, such as quartz, boron glass, sodium glass, and the like, to form a solid film to isolate the glass surface of the microchannels from the environment. Therefore, the present invention can be applied for electrophoresis experiment, so that the operation causes no electrical-double-layer effects, and further eliminates the occurrence of electro-osmosis flow, thus the separation efficiency of electrophoresis chips is improved.

Abstract: A solder ball allocation on a chip, and a method of the same are provided. The chip has a substrate, first solder balls and second solder balls. The first solder balls are located on a periphery of the substrate and arranged outwardly. The second solder balls are located in a central part of the substrate and arranged with several first geometric patterns that construct a second geometric pattern. The first geometric patterns are also arranged to divide the chip into several power source blocks. The conflict between the second solder balls and the power source blocks are analyzed to remove the second solder balls with conflicts. The power line can go through the middle directly to avoid the power source bypass, or other reasons that cause the chip unable to work stable. The invention divides the chip into several power source blocks without increase the chip volume and cost.

Abstract: A layout structure of a central processing unit (CPU) that supports two different package techniques, comprising a motherboard that comprises the layout structure and a layout method. The layout structure of the preferred embodiment according to the present invention from up to down sequentially places a top signal layer, a grounded layer, a power layer having a grounded potential, and a bottom solder layer in the area where the signals of the CPU are coupled to the signals of the control chip, so that the signals that are placed on the bottom solder layer can refer to a grounded potential area of the power layer. Therefore, part of signals of the CPU that are coupled to the control chip can be placed on the bottom solder layer.

Abstract: This invention relates to a layout structure for providing stable power supply to a four-layer motherboard and a main bridge chip substrate. In the invention, on the top signal layer and power path of the bottom solder layer for layout of the main bridge chip and on the power ring, the decoupling capacitors are connected in between the ground bonding pads/solder balls and the power bonding pads/solder balls of the power paths and power rings, so as to provide a stable power supply for the operation of the main bridge chip. In this invention, the ground bonding pad/solder ball connected with each power bonding pad/solder ball can be the closest ground bonding pad/solder ball to the power bonding pad/solder ball.

Abstract: The present invention is a placement that is utilized in a 4 layers motherboard and a main bridge chip substrate. The layout adds a placement of the power rings and the power paths on the top signal layer and the bottom solder layer of the main bridge chip on the motherboard, the second layer and the third layer are planned as grounded layers, so that all signals on the top signal layer and the bottom solder layer on the motherboard can easily refer to the grounded layer. The layout of the power ring and the power path on the top signal layer on the motherboard is symmetrical to the layout of the power ring and the power path on the bottom solder layer on the motherboard, and all power paths couple to the corresponding power rings. The power bonding pads/solder balls are arranged on the area where the power rings and the power paths pass through, and the moderate quantity of the grounded bonding pads are arranged on the both sides of the power paths.

Abstract: A chipset to support multiple CPU's and a layout method thereof. Those independent signal lines for delivering high frequency clock signals of the chipset are isolated from using by other signals without being multiplexed. Trace length of the independent signal line is shorter than that of the others. The spaces between the independent signal line and others are also larger than that between other signal lines. Signal transmission quality is significantly upgraded because the high frequency clock signal is not multiplexed and isolated from others.

Abstract: Organic electroluminescent (OEL) devices are proposed herein to be fabricated either as a light source or a heating source for biochips. Under the proposed approach, an OEL-emitting member is fabricated as the substrate of the biochip on which the biological samples, such as DNA, proteins and other related small molecules, are processed for the desired applications, including but not limited to, analysis of biological molecules, such as electrophoretic separation, PCR amplification and hybridization.

Abstract: A processing apparatus includes a processing chamber and an insertion jig for inserting an object to be processed into the processing chamber. The processing chamber and the insertion jig are adapted to be individually movable relative to a heating section, so that the operation of loading and unloading the object into and from the processing chamber effected by the insertion jig is conducted outside the heating section, thereby preventing the outside air from being induced to enter the heated processing chamber, together with the object of the processing, and thus avoiding the occurrence of various problems, for example, the object of processing being disorderly oxidized by the oxygen contained in the outside air, and the foreign matter contained in the outside air being undesirably attached to the surface of the object, so as to obtain excellent processing results.