Patents by Inventor Shu-Hung Yeh

Shu-Hung Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240147683
    Abstract: The invention provides a layout pattern of static random access memory, which comprises a plurality of fin structures on a substrate, a plurality of gate structures on the substrate and spanning the fin structures to form a plurality of transistors distributed on the substrate. The transistors include a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2) and a second pull-down transistor (PD2), a first access transistor (PG1), a second access transistor (PG2), a first read port transistor (RPD) and a second read port transistor (RPG). The gate structure of the first read port transistor (RPD) is connected to the gate structure of the first pull-down transistor (PD1), wherein a drain of the first pull-down transistor (PD1) is connected to a first voltage source Vss1, and a drain of the first read port transistor (RPD) is connected to a second voltage source Vss2.
    Type: Application
    Filed: November 27, 2022
    Publication date: May 2, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Shu-Wei Yeh, Chang-Hung Chen
  • Patent number: 11943935
    Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: March 26, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Shu-Ru Wang, Yu-Tse Kuo, Chang-Hung Chen, Yi-Ting Wu, Shu-Wei Yeh, Ya-Lan Chiou, Chun-Hsien Huang
  • Publication number: 20240087974
    Abstract: An semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill layer and an encapsulant. The first semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface and a first side surface connecting with the first bottom surface and the first top surface, the first side surface comprises a first sub-surface and a second sub-surface connected with each other, the first sub-surface is connected with the first bottom surface, and a first obtuse angle is between the first sub-surface and the second sub-surface.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Lin, Chin-Hua Wang, Shu-Shen Yeh, Chien-Hung Chen, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 7741569
    Abstract: An electronic weight scale includes: a main scale module including a main weight sensor disposed in a main housing and outputting an output corresponding to weight acting on the main housing and sensed thereby, a controller operable in one of folded and unfolded modes in response to a control signal from an input unit, and a display unit mounted on the main housing; and an auxiliary scale unit connected pivotally to the main scale module and including an auxiliary scale module that has an auxiliary weight sensor disposed in an auxiliary housing and outputting an output corresponding to weight acting on the auxiliary housing and sensed thereby. The controller outputs weight information, that indicates the output from the main weight sensor when in the folded mode and that indicates a sum of the outputs from the main and auxiliary weight sensors when in the unfolded mode, to the display unit.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: June 22, 2010
    Assignee: Shu-Te University
    Inventors: Chyun-Chau Lin, Nien-Te Liu, Shu-Hung Yeh, Chieh-I Wang
  • Publication number: 20090229889
    Abstract: An electronic weight scale includes: a main scale module including a main weight sensor disposed in a main housing and outputting an output corresponding to weight acting on the main housing and sensed thereby, a controller operable in one of folded and unfolded modes in response to a control signal from an input unit, and a display unit mounted on the main housing; and an auxiliary scale unit connected pivotally to the main scale module and including an auxiliary scale module that has an auxiliary weight sensor disposed in an auxiliary housing and outputting an output corresponding to weight acting on the auxiliary housing and sensed thereby. The controller outputs weight information, that indicates the output from the main weight sensor when in the folded mode and that indicates a sum of the outputs from the main and auxiliary weight sensors when in the unfolded mode, to the display unit.
    Type: Application
    Filed: July 18, 2008
    Publication date: September 17, 2009
    Applicant: Shu-Te University
    Inventors: Chyun-Chau Lin, Nien-Te Liu, Shu-Hung Yeh, Chieh-I Wang