Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for a multi-level turn-off circuit. An example power delivery circuit includes a two-level turn-off circuit to be coupled to a first switch to reduce a first gate voltage of the first switch from a first voltage to a second voltage when a current flowing through the first switch is greater than an over-current threshold, the two-level turn-off circuit including a second switch, a voltage-current-voltage buffer to reduce a second gate voltage of the second switch from a third voltage to a fourth voltage, and a comparator circuit to turn off the second switch when the second gate voltage is the fourth voltage, and a driver to be coupled to the first switch to turn off the first switch when the second gate voltage is the fourth voltage.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for a multi-level turn-off circuit. An example power delivery circuit includes a two-level turn-off circuit to be coupled to a first switch to reduce a first gate voltage of the first switch from a first voltage to a second voltage when a current flowing through the first switch is greater than an over-current threshold, the two-level turn-off circuit including a second switch, a voltage-current-voltage buffer to reduce a second gate voltage of the second switch from a third voltage to a fourth voltage, and a comparator circuit to turn off the second switch when the second gate voltage is the fourth voltage, and a driver to be coupled to the first switch to turn off the first switch when the second gate voltage is the fourth voltage.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for a multi-level turn-off circuit. An example power delivery circuit includes a two-level turn-off circuit to be coupled to a first switch to reduce a first gate voltage of the first switch from a first voltage to a second voltage when a current flowing through the first switch is greater than an over-current threshold, the two-level turn-off circuit including a second switch, a voltage-current-voltage buffer to reduce a second gate voltage of the second switch from a third voltage to a fourth voltage, and a comparator circuit to turn off the second switch when the second gate voltage is the fourth voltage, and a driver to be coupled to the first switch to turn off the first switch when the second gate voltage is the fourth voltage.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for a multi-level turn-off circuit. An example power delivery circuit includes a two-level turn-off circuit to be coupled to a first switch to reduce a first gate voltage of the first switch from a first voltage to a second voltage when a current flowing through the first switch is greater than an over-current threshold, the two-level turn-off circuit including a second switch, a voltage-current-voltage buffer to reduce a second gate voltage of the second switch from a third voltage to a fourth voltage, and a comparator circuit to turn off the second switch when the second gate voltage is the fourth voltage, and a driver to be coupled to the first switch to turn off the first switch when the second gate voltage is the fourth voltage.

Abstract: A buck switching voltage regulator, with high side and low side switching transistors, includes mode control circuitry for switching between PWM and PFM modes based on sensing inductor current through the low side switch during switching cycle OFF times (inductor discharge). Mode switching is based on comparing a an integrated inductor current sense signal with an integrated reference signal corresponding to a predefined average inductor current IAVE. In one embodiment, a mode switching condition is based in part on [IVALLEY=2IAVE?IPEAK], where IPEAK is a detected peak inductor current at the beginning of an OFF time, and IVALLEY is an inductor current value determined by IAVE and IPEAK.

Abstract: Mode control circuitry is disclosed for use in a buck switching voltage regulator capable of operating in a pulse width modulation (PWM) mode and a pulse frequency modulation (PFM) mode, with the regulator including an inductor having first and second opposite inductor terminals, a first transistor switch connected between the first inductor terminal and a power input terminal and a second transistor switch connected between the first inductor terminal and a circuit common. Current sensing circuitry is provided to sense inductor current through the second switching transistor when the second switching transistor is switched to an ON state and to produce a current sense signal which is integrated over time starting when the second switching transistor is switched to an ON state and to produce a sense signal. The mode switching circuitry switches between the PWM and PFM modes in response to the sense signal.

Abstract: A buck switching voltage regulator, with high side and low side switching transistors, includes mode control circuitry for switching between PWM and PFM modes based on sensing inductor current through the low side switch during switching cycle OFF times (inductor discharge). Mode switching is based on comparing a an integrated inductor current sense signal with an integrated reference signal corresponding to a predefined average inductor current IAVE. In one embodiment, a mode switching condition is based in part on [IVALLEY=21AVE?IPEAK], where IPEAK is a detected peak inductor current at the beginning of an OFF time, and IVALLEY is an inductor current value determined by IAVE and IPEAK.

Abstract: Mode control circuitry is disclosed for use in a buck switching voltage regulator capable of operating in a pulse width modulation (PWM) mode and a pulse frequency modulation (PFM) mode, with the regulator including an inductor having first and second opposite inductor terminals, a first transistor switch connected between the first inductor terminal and a power input terminal and a second transistor switch connected between the first inductor terminal and a circuit common. Current sensing circuitry is provided to sense inductor current through the second switching transistor when the second switching transistor is switched to an ON state and to produce a current sense signal which is integrated over time starting when the second switching transistor is switched to an ON state and to produce a sense signal. The mode switching circuitry switches between the PWM and PFM modes in response to the sense signal.

Abstract: The invention relates to a switching regulator with an error amplifier circuit and a feed-forward circuit. The error amplifier circuit provides an error signal by amplifying the difference between a feedback signal and a reference signal. The feed-forward circuit level-shifts the output of the error amplifier based on the feed-forward input signal and a scaling factor. The resulting adjusted error signal includes both feed-back and feed-forward signal components. A PWM comparator is employed to compare the adjusted error signal to a ramp signal. Switched-mode regulation is performed based on the PWM comparator output. In addition, buck-boost mode transition smoothing circuitry may also be employed to smooth the buck-mode/boost-mode transition in a buck-boost switching regulator.

Abstract: Adjustable gain circuits (AGCs) within serial filter stages are initialized to maximum gain. The output of each AGC is then sampled and converted to digital representation for use by control logic in setting the gain for the respective AGC. The gain adjustment decision for each AGC is performed in one shot, sequentially backwards from the last AGC, such that gain may be adapted simply and quickly within a number of cycles equal to the number of AGCs. Performance is enhanced by a fast-adapting cell in which capacitances are switched into the input path and feedback loop of an amplifier to reduce direct current gain within the transfer function through charge sharing dividing down the output voltage.

Abstract: A PWM buck-or-boost converter is provided. The converter includes an error amplifier, a rectifier/splitter, a first comparator, and a second comparator. The rectifier/splitter provides two signals proportional to the departure of the error voltage from a central value but increasing in value from zero. Only one of the two signals departs from zero depending on the error voltage. The first comparator compares one of the two signals to a modulating waveform (e.g. a sawtooth waveform), and the second comparator compares the other of the two signals to the modulating waveform. Only one of the two signals intersects the modulating waveform depending on the error voltage. During buck regulation, the first comparator controls the buck switches and the output of the second comparator remains high. During boost regulation, the second comparator controls the boost switches and the output of the first comparator remains high.

Abstract: The invention relates to a differential amplifier with internal compensation. The invention also relates to a regulator controller and a regulator which includes such an amplifier. The amplifier includes a preamplifier circuit and a gain circuit. The frequency response of the amplifier is based in part on internal compensation within the preamplifier circuit. The internal compensation of the differential amplifier includes a low frequency zero that is provided by the preamplifier circuit.

Abstract: A PFM buck-or-boost converter is provided. The converter includes, inter alia, a hysteretic comparator, current sense circuitry, a logic circuit, drivers, current sense circuitry, a first buck switch, and a first boost switch. The current sense circuitry asserts signal Z if the current through the boost switch (from the load to the inductor) is greater than zero, and unasserts Z otherwise. Additionally, the current sense circuitry asserts signal I if the current through the buck switch is greater than a fixed current limit value, and unasserts I otherwise. The logic circuit employs the hysteretic comparator output, signal Z, and signal I to control the switches, and to determine whether to operate in buck regulation mode or boost regulation mode.

Abstract: Rejection of local oscillator harmonic response is provided in a mixing circuit with a pair of harmonic gating switches serially connected to the outputs of a balanced differential switching mixer and controlled by a gate clock signal having twice the frequency of a local oscillator signal controlling the switching mixer. An aperture or duty cycle of the gate clock signal determines which harmonic is rejected or suppressed, which is preferably a third and/or fifth harmonic since response of the balanced differential switching mixer to even harmonics is negligible. The resulting simple, efficient circuit is readily integrated directly into a phase-alternating mixer structure for a chopper-direct-conversion radio.

Abstract: Rejection of local oscillator harmonic response is provided in a mixing circuit with a pair of harmonic gating switches serially connected to the outputs of a balanced differential switching mixer and controlled by a gate clock signal having twice the frequency of a local oscillator signal controlling the switching mixer. An aperture or duty cycle of the gate clock signal determines which harmonic is rejected or suppressed, which is preferably a third and/or fifth harmonic since response of the balanced differential switching mixer to even harmonics is negligible. The resulting simple, efficient circuit is readily integrated directly into a phase-alternating mixer structure for a chopper-direct-conversion radio.

Abstract: A phase alternating mixer is implemented by common-base differential transistor pairs, with two cross-coupled pairs providing a switching mixer function with harmonic gating suppression of harmonic responses to the switching mixing by control of local oscillator signals controlling switching of the differential transistor pairs. Rather than a resistive load, a switched capacitance load and integrating capacitors are connected to the output of the differential transistor pairs to provide first order low pass filtering of the double sideband output from the differential pairs, with a controlled bandwidth. Channel select switches demultiplex the double sideband signal into a baseband signal.

Abstract: A radio frequency (RF) receiver comprising: 1) a local oscillator (LO) circuit capable of receiving a local oscillator (LO) reference signal having frequency, LO, and a double sideband (DSB) clock signal having a frequency, DSB, and generating therefrom an in-phase product signal of the LO reference signal and the DSB clock signal in which a polarity of the LO reference signal is reversed at the DSB frequency of the DSB clock signal; and 2) a first radio frequency (RF) mixer having a first input port capable of receiving the in-phase product signal from the LO circuit and a second input port capable of receiving a modulated radio frequency (RF) signal, wherein the first RF mixer generates a first downconverted output signal.

Abstract: A radio frequency (RF) demodulation circuit comprising a harmonic rejection mixing stage capable of receiving and mixing an incoming radio frequency (RF) signal having a frequency RF and a reference local oscillator (LO) signal having a frequency LO and generating an output signal in which out-of-band harmonic signals are suppressed. The harmonic rejection mixing stage comprises 1) a multiphase local oscillator (LO) generator for receiving the reference LO signal and generating M phase-shifted local oscillator signals having frequencies LO and 2) M mixers, each of the M mixers receiving the incoming radio frequency signal and one of the M phase-shifted local oscillator signals. Each of the M mixers generates a subcomponent signal. The subcomponent signals are then scaled and combined to produce the output signal.

Abstract: A RF down/up-conversion circuit comprising: 1) a local oscillator chopping circuit comprising: a) a frequency divider circuit for receiving a first local oscillator (LO) signal having a frequency of LO and generating a frequency-divided second local oscillator (LO) signal having a frequency of LO/N and synchronized with the first LO signal; and b) a multiplier for receiving the first and second LO signals and generating a product signal of the first and second LO signals; and 2) a differential radio frequency (RF) mixer having a first differential input port for receiving the product signal from the multiplier and a second differential input port for receiving a first differential modulated radio frequency (RF) signal and a second differential modulated radio frequency (RF) signal, wherein the differential RF mixer generates a differential output signal.

Abstract: An integrated switched capacitor bias circuit for generating a reference signal which is proportional to absolute temperature, a capacitance and a clock signal frequency. A current mirror circuit generates a primary current and a mirrored current. Under the control of a clock signal, a switched capacitor circuit uses the mirrored current to constantly accumulate charges on primary capacitor while also alternately sharing such charges with and then discharging one of two additional capacitors. The magnitude of the current drawn by the switched capacitor circuit is a factor of the junction area of a diode and absolute temperature. To maintain equality of the primary and mirrored currents, a node voltage within the current mirror circuit is monitored by a bias circuit which provides a bias signal for controlling the current mirror circuit.