Abstract: The present disclosure relates to a driving method and a driving unit of GOA circuits. The driving unit includes a timing control chip and a GOA circuit including a plurality of cascaded GOA driving units. The timing control chip inputs first clock signals, second clock signals, and a constant-voltage potential to the GOA driving units at each of levels to drive the GOA driving units to output the scanning driving signals level-by-level, wherein scanning initial signals are further inputted to the GOA driving units at the first through the fourth level. The first clock signals and the second clock signals are two different clock signals selected from one clock signals set including eight high-frequency clock signals (CK1˜CK8), wherein CKm and CKm+4 are inverting signals.

Abstract: A display panel and a display device are disclosed. The display panel includes a first control signal unit for outputting multiple first control signals; a second control signal unit for outputting multiple second control signals, wherein the multiple first control signals and the multiple second control signals are the same; and a first scanning driving circuit connected with the first control signal unit and the second control signal unit, and used for receiving the multiple first control signals from the first control signal unit, receiving the multiple second control signals from the second control signal unit and outputting a first scanning signal in order to reduce the RC load, avoid the abnormality of the waveform of the output scanning signal so as to improve the display quality.

Abstract: The present disclosure relates to a driving method and a driving unit of GOA circuits. The driving unit includes a timing control chip and a GOA circuit including a plurality of cascaded GOA driving units. The timing control chip inputs first clock signals, second clock signals, and a constant-voltage potential to the GOA driving units at each of levels to drive the GOA driving units to output the scanning driving signals level-by-level, wherein scanning initial signals are further inputted to the GOA driving units at the first through the fourth level. The first clock signals and the second clock signals are two different clock signals selected from one clock signals set including eight high-frequency clock signals (CK1˜CK8), wherein CKm and CKm+4 are inverting signals.

Abstract: The present application discloses a pull down maintaining circuit, comprising: a first switch transistor, an input terminal is connected to a first direct current power source, and an output terminal outputting a scanning signal of the Nth level scanning line; a second switch transistor, an input terminal is connected to the first direct current power source, and an output terminal outputting a scanning electric level signal of the Nth level scanning line; a control unit for controlling the first and the second switch transistors to turn off in accordance with a low voltage outputted from the first and the second direct current power source, and the third direct current power source, and to control the first and the second switch transistors to normally turn on in accordance with a high voltage is outputted from the first and the second direct current power source, and the third direct current power source.

Abstract: The present disclosure relates to a gate driving circuit including N number of cascaded-connected GOA driving units, wherein the GOA driving units at each of the levels includes a pull-up control circuit, a pull-up circuit, a level transfer circuit, a boast capacitor, and a pull-down holding circuit. The pull-down holding circuit of the GOA driving unit of the n-th level and the pull-down holding circuit of the GOA driving unit of the (n+1)-th level are turned on alternatedly. The pull-down holding circuit of die GOA driving unit of the n-th level may keep the potential of the node within the GOA driving units at the n-th and the (n+1)-th level in the off state, wherein n=1, 3, 5, . . . , N?1, and N is an even number greater than one. The present disclosure also relates to a LCD including the above gate driving circuit.

Abstract: The present disclosure provides a GOA circuit and a liquid crystal display, the GOA circuit includes: a pull-up circuit; a scan output terminal; a pull-up control circuit including: a second switch tube; a third switch tube having a first connection terminal coupled to the second connection terminal of the second switch tube and a second connection terminal coupled to the control terminal of the first switch tube; a fourth switch tube having a control terminal coupled to the control terminal of the first switch tube, a first connection terminal coupled to the first connection terminal of the third switch tube and a second connection terminal coupled to the scan output terminal. In this way, the disclosure can avoid the problem that the transistor is erroneously turned on or off due to the threshold drift and the circuit output error is caused.

Abstract: A display assembly includes an array of display elements disposed between a first substrate and a second substrate, the array of display elements including one or more thin film transistors (TFTs). A black mask arrangement is disposed between the first substrate and the second substrate, the black mask arrangement being configured to prevent light entering the display assembly from reaching the TFTs.