Abstract: A method of forming a gate oxide layer is disclosed, which introduces a rapid laser annealing process, performed on the surface of the gate SiON layer, prior to a high-temperature annealing process performed on the gate SiON layer. This enables the method of the invention to remove the intrinsic oxide layer, protect the doped nitrogen atoms from the adverse influence of organic absorption, and lead to the formation of an amorphized surface layer which is able to prevent nitrogen atoms located around the surface from escaping by volatilization and nitrogen atoms beneath the surface from diffusing towards the SiO2/Si boundary. Therefore, the gate SiON layer formed by the method of the invention can ensure a high and stable nitrogen content, thus achieving the objective to obtain a gate SiON layer with a more precisely trimmed dielectric constant and hence improve the electrical properties of the semiconductor device being fabricated.

Abstract: A method of forming a ?-shaped trench is disclosed. The method includes: providing a silicon substrate; and performing a plasma etching process to form a ?-shaped trench in the silicon substrate. The plasma etching process includes: etching the silicon substrate using a first plasma etching gas including a sulphur-containing fluoride; and etching the silicon substrate using a second plasma etching gas including a sulphur-containing fluoride and a polymer gas. A method of forming a semiconductor device is also disclosed.

Abstract: A method of forming a ?-shaped trench is disclosed. The method includes: providing a silicon substrate; and sequentially performing a plasma etching process and a wet etching process on the silicon substrate to form a ?-shaped trench therein. The plasma etching process includes: horizontally etching the silicon substrate using a first plasma etching gas including a nitrogen-containing fluoride; and vertically etching the silicon substrate using a second plasma etching gas including a polymer gas. A method of forming a semiconductor device is also disclosed.

Abstract: A method for forming a low voltage coefficient capacitor. A doped polysilicon layer is formed in a region predetermined to form a capacitor and a doped polysilicon layer is formed in a region predetermined to form a gate. A silicide layer is formed on the doped polysilicon layer serving as a bottom electrode of a capacitor.

Abstract: A semiconductor fabrication method is provided for fabricating a capacitor with a low-resistance electrode structure in a mixed-mode integrated circuit (IC) device. The first step is to prepare a semiconductor substrate having a first area where a gate and a pair of source/drain regions are defined and a second area where a first electrode is defined. A first dielectric layer is then formed to cover the first electrode. After this, a doped polysilicon layer, a metal silicide layer, and a second dielectric layer are successively formed over the first dielectric layer, which in combination constitute a second electrode for the capacitor. The incorporation of the metal silicide layer in the second electrode can significantly help reduce the overall resistance of the second electrode, thereby allowing a considerable increase to the overall performance of the resulting IC device. Moreover, the method is less complex in process and thus easier to perform than the prior art.