Abstract: A user equipment (UE) is configured to join a multicast broadcast service (MBS) session. The UE sends, to a network function, a protocol data unit (PDU) modification request comprising a request to join a multicast broadcast service (MBS) session, generates a first key (KMBS-UE), receives a PDU session modification complete message comprising an encrypted second key (KMBS) and a key identification (KID) corresponding to the KMBS and decrypts the Kiss using the KMBS-UE.

Abstract: A method for producing graphene, configured for forming a graphene layer on a surface of an object. The method includes steps of: depositing a poly-p-xylene material layer on the surface: and converting the poly-p-xylene material layer into a graphene layer by using a laser sintering process or a plasma-assisted sintering process.

Abstract: A docking structure includes a first base and a second base connected to the first base; a first electrode group arranged in parallel and combined on an insulating block; and a second electrode group arranged in parallel with the first electrode group, wherein the second electrode group is used for bonding the first electrode group, the second electrode group is combined with the first base and has freedom in a first direction, moves in the first direction by a first elastic structure; the first base is combined with the second base and has freedom in a second direction different from the first direction. A second elastic structure is connected between the first and second bases. A first plane of the first electrode group and a second plane of the second electrode group are kept in parallel surface contact during docking the first and second electrode groups.

Abstract: A base die is configured to receive first data and first encoded data in a writing phase, perform first error checking and correction processing, wherein the first encoded data is obtained by performing a first error correction code encoding processing on the first data, and transmit second data to a memory die in the writing phase, wherein the second data includes a first data after the first error checking and correction processing; the base die is further configured to receive the second data from the memory die in a reading phase, perform second error correction code encoding processing on the second data to generate second encoded data, and transmit third data in the reading phase, wherein the third data includes the second encoded data and the first data after the first error checking and correction processing.

Abstract: Embodiments of the disclosure, there is provided a method, a system for adjusting the memory, and a semiconductor device. The method for adjusting the memory includes: acquiring a mapping relationship between a temperature of a transistor, an equivalent width-length ratio of a sense amplifier transistor in a sense amplifier and an actual time at which the data is written into the memory; acquiring a current temperature of the transistor; and adjusting the equivalent width-length ratio, based on the current temperature and the mapping relationship, so that the actual time at which the data is written into the memory corresponding to the adjusted equivalent width-length ratio is within a preset writing time.

Abstract: A base die is configured to: receive first data in a writing phase, perform error correction code encoding processing to generate encoded data, and transmit second data to a memory die in the writing phase, wherein the second data includes the first data and the encoded data; and receive the second data from the memory die in a reading phase, perform error checking and correction processing, and transmit third data in the reading phase, wherein the third data is the first data after the error checking and correction processing.

Abstract: A user equipment (UE) may attempt to access an edge data network. The UE generates a first credential based on a second credential that was generated for a procedure between the UE and a network. The UE then generates an identifier corresponding to the first credential and generates a message authentication code based on the first credential and a count, wherein the count is associated with an identifier of an edge network client running on the UE. The UE then transmits an application registration request, message to a server associated with an edge data network, the application registration request message including the count, the message authentication code, the identifier corresponding to the first credential, and a public land mobile network identifier (PLMN ID) of the network. The UE then receives an authentication accept message or an authentication reject message from the server associated with the edge data network.

Abstract: A network may authenticate a user equipment (UE) to access an edge data network. The network generates a first credential based on a second credential, the second credential generated for a procedure between the UE and a cellular network corresponding to the network component, receives an identifier associated with the first credential from a further network component in response to the UE transmitting an application registration request to a server associated with an edge data network and retrieves the first credential based on the identifier. The network also receives a multi-access edge computing (MEC) authorization parameter, verifies the MEC authorization parameter and transmits an authentication verification response to a second network component.

Abstract: A user equipment (UE) configured to connect to an edge data network. The UE connects to a first edge application server (EAS) of an edge data network (EDN), the connecting comprising performing a first authorization/authentication procedure, receives a message indicating the UE is to connect to a second EAS of the EDN, the message including an indication as to whether the UE is to perform a second authorization/authentication procedure to connect to the second EAS and performs a discovery procedure to locate the second EAS based on at least the indication in the message.

Abstract: A method for fabricating semiconductor devices includes forming channel regions over a substrate. The channel regions, in parallel with one another, extend along a first lateral direction. Each channel region includes at least a respective pair of epitaxial structures. The method includes forming a gate structure over the channel regions, wherein the gate structure extends along a second lateral direction. The method includes removing, through a first etching process, a portion of the gate structure that was disposed over a first one of the channel regions. The method includes removing, through a second etching process, a portion of the first channel region. The second etching process includes one silicon etching process and one silicon oxide deposition process. The method includes removing, through a third etching process controlled based on a pulse signal, a portion of the substrate that was disposed below the removed portion of the first channel region.

Abstract: A vinyl-containing copolymer is copolymerized from (a) first compound, (b) second compound, and (c) third compound. (a) First compound is an aromatic compound having a single vinyl group. (b) Second compound is polybutadiene or polybutadiene-styrene having side vinyl groups. (c) Third compound is an acrylate compound. The vinyl-containing copolymer includes 0.003 mol/g to 0.010 mol/g of benzene ring, 0.0005 mol/g to 0.008 mol/g of vinyl group, and 1.2*10?5 mol/g to 2.4*10?4 mol/g of ester group.

Abstract: A method for predicting clinical severity of a neurological disorder includes steps of: a) identifying, according to a magnetic resonance imaging (MRI) image of a brain, brain image regions each of which contains a respective portion of diffusion index values of a diffusion index, which results from image processing performed on the MRI image; b) for one of the brain image regions, calculating a characteristic parameter based on the respective portion of the diffusion index values; and c) calculating a severity score that represents the clinical severity of the neurological disorder of the brain based on the characteristic parameter of the one of the brain image regions via a prediction model associated with the neurological disorder.

Abstract: A carrier structure is provided with a plurality of package substrates connected via connecting sections, and a functional element and a groove are formed on the connecting section, such that the groove is located between the package substrate and the functional element. Therefore, when a cladding layer covering a chip is formed on the package substrate, the groove can accommodate a glue material overflowing from the cladding layer to prevent the glue material from contaminating the functional element.

Abstract: Embodiments of this application provide a method and system for adjusting a memory, and a semiconductor device. The method for adjusting a memory includes: acquiring a mapping relationship among a temperature of a transistor, a substrate bias voltage of a sense amplification transistor in a sense amplifier, and an actual data writing time of the memory; acquiring a current temperature of the transistor; and adjusting the substrate bias voltage on the basis of the current temperature and the mapping relationship, such that an actual data writing time corresponding to an adjusted substrate bias voltage is within a preset writing time.

Abstract: The present application relates to devices and components including apparatus, systems, and methods for secured user equipment communications over a user equipment relay. In some embodiments, symmetric or asymmetric encryption may be used for the secured user equipment communications.

Abstract: Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.

Abstract: A memory chip is applied to the memory system, and the memory chip is configured to perform counting and obtain a count value after the memory chip is powered on and started, wherein the count value is used to represent a process corner of the memory chip, the memory chip further has a reference voltage with an adjustable value, the value of the reference voltage is adjustable based on the count value, and the memory chip adjusts, based on the reference voltage, a delay from reading out data from a memory cell to outputting the data through a data port.

Abstract: A memory is provided. The memory includes: a control chip; and a plurality of storage chips, in which the plurality of storage chips are electrically connected with the control chip via a common communication channel, the plurality of storage chips are configured to perform information interaction with the control chip by adopting different clock edges of a first clock signal, the first clock signal has a first clock cycle, the different clock edges include two consecutive rising edges and/or two consecutive falling edges, the plurality of storage chips are further configured to receive a second clock signal and distinguish the different clock edges based on the second clock signal, and a second clock cycle of the second clock signal is greater than the first clock cycle.

Abstract: A memory system includes: a plurality of memory chips, wherein each of the memory chips has a parameter used to characterize a process corner of the memory chip; and a controller, wherein the controller is configured to: obtain the parameter of each of the memory chips, and adjust, based on the parameter, a delay of a read command sent to the memory chip corresponding to the parameter.

Abstract: A memory includes: a control chip; and a plurality of storage chips, in which the plurality of storage chips are electrically connected with the control chip via a common communication channel, the plurality of storage chips include a first storage chip set and a second storage chip set, the storage chips in the first storage chip set are configured to perform information interaction with the control chip by adopting a first clock signal, the storage chips in the second storage chip set are configured to perform information interaction with the control chip by adopting a second clock signal, and phase of the first clock signal is different from phase of the second clock signal.