Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.

Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a sacrificial layer over the semiconductor substrate, etching the sacrificial layer to form a sacrificial pattern, etching the semiconductor substrate using the sacrificial pattern as an etching mask to form an active region of the semiconductor substrate, trimming the sacrificial pattern, and replacing the trimmed sacrificial pattern with a gate electrode.

Abstract: A defrosting lens includes a lens barrel having an opening toward an object side, a first lens disposed in the lens barrel and located at the opening, and a heating member. The heating member is for providing a heat source and is disposed between an inner wall of the lens barrel and the first lens. The heating member is arranged along a peripheral edge of the first lens. By raising a temperature of the first lens through the heat source supplied by the heating member, frost formed on the first lens could be removed, thereby a definition of an image captured by the defrosting lens could be effectively improved, and the defrosting lens could be applied in various environments without being limited by the change of climate temperature difference.

Abstract: A method includes forming a stack of material layers to cover an array region and a periphery region of a substrate. A first patterned mask layer is formed, and the pattern of the first patterned mask layer is transferred to the stack of material layers, thereby forming a first array pattern and a first periphery pattern respectively in the array and periphery regions. A second patterned mask layer is provided above the first array and periphery patterns. The pattern of the second patterned mask is not aligned with the pattern of the first patterned mask. The pattern of the second patterned mask layer is transferred to form the first and second sacrificial patterns respectively in the array and periphery regions. The first array pattern, the first and second sacrificial patterns, and the first periphery pattern are simultaneously transferred to form a second array pattern and a second periphery pattern.

Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a sacrificial layer over the semiconductor substrate, etching the sacrificial layer to form a sacrificial pattern, etching the semiconductor substrate using the sacrificial pattern as an etching mask to form an active region of the semiconductor substrate, trimming the sacrificial pattern, and replacing the trimmed sacrificial pattern with a gate electrode.

Abstract: A method includes forming a stack of material layers to cover an array region and a periphery region of a substrate. A first patterned mask layer is formed, and the pattern of the first patterned mask layer is transferred to the stack of material layers, thereby forming a first array pattern and a first periphery pattern respectively in the array and periphery regions. A second patterned mask layer is provided above the first array and periphery patterns. The pattern of the second patterned mask is not aligned with the pattern of the first patterned mask. The pattern of the second patterned mask layer is transferred to form the first and second sacrificial patterns respectively in the array and periphery regions. The first array pattern, the first and second sacrificial patterns, and the first periphery pattern are simultaneously transferred to form a second array pattern and a second periphery pattern.

Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes a substrate, a plurality of first gate structures, a first dielectric layer, a second dielectric layer, a third dielectric layer and a contact plug. The first gate structures are formed on an array region of the substrate. The first dielectric layer is formed on top surfaces and sidewalls of the first gate structures. The second dielectric layer is formed on the first dielectric layer and in direct contact with the first dielectric layer. The second dielectric layer and the first dielectric layer are made of the same material. The third dielectric layer is formed between the first gate structures and defines a plurality of contact holes exposing the substrate. The contact plug fills the contact holes.

Abstract: A memory device includes a substrate, a bit line, a first insulating film, a second insulating film, a third insulating film, and a contact. The bit line is disposed over the substrate. The first insulating film is disposed on a sidewall of the bit line. The second insulating film is disposed on the first insulating film and is made of a different material than the first insulating film. The third insulating film is disposed on the second insulating film and is made of a different material than the second insulating film. The top surfaces of the second insulating film and the third insulating film are lower than the top surface of the first insulating film. The contact is disposed over the substrate and adjacent to the bit line. The width of the lower portion of the contact is less than the width of the upper portion of the contact.

Abstract: An anti-theft zipper includes a first zipper slider, a first zipper puller, a second zipper slider, and a second zipper puller. The first zipper puller has a first connecting end, a first locking end, a first locking ring, and a first engaging portion. The first connecting end is connected to the first zipper slider. The first locking ring is disposed on the first locking end. The first engaging portion is formed on the first zipper puller. The second zipper puller has components and configuration corresponding to those of the first zipper puller. The first engaging portion engages with a second engaging portion of the second zipper puller, preventing the first zipper puller and the second zipper puller from rotating and moving relative to each other. A luggage lock includes the anti-theft zipper and a locking assembly locking the first locking ring and a second locking ring of the anti-theft zipper.

Abstract: A semiconductor structure and its manufacturing method are provided. A semiconductor structure includes a substrate and several bit lines on the substrate. Each of the bit lines includes a first conductive layer on the substrate, a second conductive layer on the first conductive layer, and a hardmask layer on the second conductive layer. The semiconductor structure further includes several contacts disposed on the substrate and positioned between two adjacent bit lines, wherein the bottom surfaces of the contacts physically contact the substrate. The top surfaces of the contacts are not higher than the top surfaces of the hardmask layers. Each of the contacts includes a bottom contact part on the substrate and a top contact part on the bottom contact part, and a width of a top surface of the top contact part is greater than a width of a top surface of the bottom contact part.

Abstract: A memory device includes a substrate, a bit line, a first insulating film, a second insulating film, a third insulating film, and a contact. The bit line is disposed over the substrate. The first insulating film is disposed on a sidewall of the bit line. The second insulating film is disposed on the first insulating film and is made of a different material than the first insulating film. The third insulating film is disposed on the second insulating film and is made of a different material than the second insulating film. The top surfaces of the second insulating film and the third insulating film are lower than the top surface of the first insulating film. The contact is disposed over the substrate and adjacent to the bit line. The width of the lower portion of the contact is less than the width of the upper portion of the contact.

Abstract: An anti-theft zipper includes a first zipper slider, a first zipper puller, a second zipper slider, and a second zipper puller. The first zipper puller has a first connecting end, a first locking end, a first locking ring, and a first engaging portion. The first connecting end is connected to the first zipper slider. The first locking ring is disposed on the first locking end. The first engaging portion is formed on the first zipper puller. The second zipper puller has components and configuration corresponding to those of the first zipper puller. The first engaging portion engages with a second engaging portion of the second zipper puller, preventing the first zipper puller and the second zipper puller from rotating and moving relative to each other. A luggage lock includes the anti-theft zipper and a locking assembly locking the first locking ring and a second locking ring of the anti-theft zipper.

Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a sacrificial layer over the semiconductor substrate, etching the sacrificial layer to form a sacrificial pattern, etching the semiconductor substrate using the sacrificial pattern as an etching mask to form an active region of the semiconductor substrate, trimming the sacrificial pattern, and replacing the trimmed sacrificial pattern with a gate electrode.

Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes a substrate, a plurality of first gate structures, a first dielectric layer, a second dielectric layer, a third dielectric layer and a contact plug. The first gate structures are formed on an array region of the substrate. The first dielectric layer is formed on top surfaces and sidewalls of the first gate structures. The second dielectric layer is formed on the first dielectric layer and in direct contact with the first dielectric layer. The second dielectric layer and the first dielectric layer are made of the same material. The third dielectric layer is formed between the first gate structures and defines a plurality of contact holes exposing the substrate. The contact plug fills the contact holes.

Abstract: A suitcase has a body and two zippers. The body has two openings defined in a surface of the body. The two zippers are mounted respectively in the openings of the body and are defined respectively as a first zipper and a second zipper. The first zipper has two collar pullers. The second zipper has two elongated pullers selectively extending through the collar pullers of the first zipper, and each elongated puller of the second zipper has a locking hole defined in the elongated puller.

Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes a substrate, a plurality of first gate structures, a first dielectric layer, a second dielectric layer, a third dielectric layer and a contact plug. The first gate structures are formed on an array region of the substrate. The first dielectric layer is formed on top surfaces and sidewalls of the first gate structures. The second dielectric layer is formed on the first dielectric layer and in direct contact with the first dielectric layer. The second dielectric layer and the first dielectric layer are made of the same material. The third dielectric layer is formed between the first gate structures and defines a plurality of contact holes exposing the substrate. The contact plug fills the contact holes.

Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes two first gate structures and a multilayer insulating structure. The multilayer insulating structure includes a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer sequentially from bottom to top. The width of the second insulating layer is equal to that of the third insulating layer, and smaller than that of the first insulating layer. The width of the bottom surface of the fourth insulating layer is greater than the width of the top surface of the third insulating layer. The memory device includes a capacitor contact plug formed between the first gate structures. The capacitor contact plug includes a first contact element, a buffering layer, and a second contact element. The second contact element has a top surface wider than its bottom surface.

Abstract: A suitcase has a body and two zippers. The body has two openings defined in a surface of the body. The two zippers are mounted respectively in the openings of the body and are defined respectively as a first zipper and a second zipper. The first zipper has two collar pullers. The second zipper has two elongated pullers selectively extending through the collar pullers of the first zipper, and each elongated puller of the second zipper has a locking hole defined in the elongated puller.

Abstract: A suitcase has a body and two zippers. The body has a first casing, a second casing, a middle layer, and a computer bag. The first casing has a side edge and a division layer mounted in the first casing to divide the first casing into two holding spaces. The second casing has a side edge connected with the side edge of the first casing and a division layer mounted in the second casing to divide the second casing into two holding spaces. The middle layer is mounted between the first casing and the second casing. The computer bag is mounted on the middle layer at a side facing one of the first and second casings. The two zippers are mounted between the first and second casings and the middle layer.

Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes a substrate, a plurality of first gate structures, a first dielectric layer, a second dielectric layer, a third dielectric layer and a contact plug. The first gate structures are formed on an array region of the substrate. The first dielectric layer is formed on top surfaces and sidewalls of the first gate structures. The second dielectric layer is formed on the first dielectric layer and in direct contact with the first dielectric layer. The second dielectric layer and the first dielectric layer are made of the same material. The third dielectric layer is formed between the first gate structures and defines a plurality of contact holes exposing the substrate. The contact plug fills the contact holes.