Abstract: Antigen-binding domains that are capable of binding to CD3 and CD137 but do not bind to CD3 and CD137 at the same time and methods of using the same are provided. Methods to obtain antigen binding domains which bind to two or more different antigen more efficiently are also provided.

Abstract: A non-volatile semiconductor memory and three or more types of transistors are provided. A thickness of a first gate oxide film of a first transistor is larger than that of a second gate oxide film of a second transistor, and is smaller than that of a third gate oxide film of a third transistor. In a first transistor region, a first silicon oxide film is formed on a surface of a semiconductor substrate, and second and third silicon oxide films are formed on the first silicon oxide film. By removing the second and third silicon oxide films and a part of an upper layer of the first silicon oxide film, the first gate oxide film is formed from the first silicon oxide film.

Abstract: A non-volatile semiconductor memory and three or more types of transistors are provided. A thickness of a first gate oxide film of a first transistor is larger than that of a second gate oxide film of a second transistor, and is smaller than that of a third gate oxide film of a third transistor. In a first transistor region, a first silicon oxide film is formed on a surface of a semiconductor substrate, and second and third silicon oxide films are formed on the first silicon oxide film. By removing the second and third silicon oxide films and a part of an upper layer of the first silicon oxide film, the first gate oxide film is formed from the first silicon oxide film.

Abstract: System and method for achieving reproducibility of a simulation operation while reasonably keeping an operation speed. A peripheral scheduler clears completion flags of all the peripheral emulators to thereby start parallel operations thereof. Then, based on processing break timing set for the individual peripheral emulators, the peripheral scheduler finds one of the peripheral emulators which is scheduled to reach a processing break at the earliest. The found peripheral emulator is referred to as a peripheral P. In a case where a time of the processing break of the peripheral P is T, the peripheral scheduler continues execution of processor emulators and plant simulators up until a time point of the time T. The peripheral scheduler waits for setting of a completion flag of the peripheral P. In response to the setting, the peripheral scheduler performs data synchronization among the peripheral P, the processor emulators, and the plant simulators.

Abstract: A technique for increasing the speed of parallel running of logical processes without sacrificing the accuracy of data update timing in a parallel discrete event simulation system. A logical process involving a longer receiving time lag than that of sending is executed by an amount of initial shift for a predetermined period before the simulation. The initial shift is set to be one-half of a value of difference between the receiving time lag and the sending time lag. The logical process executed with timing displaced by the amount of initial shift runs by exchanging null messages with each other. Each null message is delivered to a correspondent logical process after the predetermined time lag, and each logical process further sends the correspondent logical process a null message upon receipt of the null message. Thus, there is a progression of simulation by synchronizing them through the null messages.

Abstract: System and method for achieving reproducibility of a simulation operation while reasonably keeping an operation speed. A peripheral scheduler clears completion flags of all the peripheral emulators to thereby start parallel operations thereof. Then, based on processing break timing set for the individual peripheral emulators, the peripheral scheduler finds one of the peripheral emulators which is scheduled to reach a processing break at the earliest. The found peripheral emulator is referred to as a peripheral P. In a case where a time of the processing break of the peripheral P is T, the peripheral scheduler continues execution of processor emulators and plant simulators up until a time point of the time T. The peripheral scheduler waits for setting of a completion flag of the peripheral P. In response to the setting, the peripheral scheduler performs data synchronization among the peripheral P, the processor emulators, and the plant simulators.

Abstract: An isolation oxide film whose upper surface is higher than a surface of a substrate is formed in the substrate. A silicon oxide film is formed on the substrate between the isolation oxide films. A self-aligned polysilicon film is formed on the silicon oxide film between the isolation oxide films. After forming a resist pattern covering the peripheral circuitry, the isolation oxide films in the memory cell are etched by a predetermined thickness. An ONO film is formed on the entire surface of the substrate, a second resist pattern covering the memory cell is formed. Then, the ONO film, the polysilicon film 8 and the silicon oxide film 7 are removed from the peripheral circuitry.

Abstract: An isolation oxide film whose upper surface is higher than a surface of a substrate is formed in the substrate. A silicon oxide film is formed on the substrate between the isolation oxide films. A self-aligned polysilicon film is formed on the silicon oxide film between the isolation oxide films. After forming a resist pattern covering the peripheral circuitry, the isolation oxide films in the memory cell are etched by a predetermined thickness. An ONO film is formed on the entire surface of the substrate, a second resist pattern covering the memory cell is formed. Then, the ONO film, the polysilicon film 8 and the silicon oxide film 7 are removed from the peripheral circuitry.

Abstract: An isolation oxide film whose upper surface is higher than a surface of a substrate is formed in the substrate. A silicon oxide film is formed on the substrate between the isolation oxide films. A self-aligned polysilicon film is formed on the silicon oxide film between the isolation oxide films. After forming a resist pattern covering the peripheral circuitry, the isolation oxide films in the memory cell are etched by a predetermined thickness. An ONO film is formed on the entire surface of the substrate, a second resist pattern covering the memory cell is formed. Then, the ONO film, the polysilicon film 8 and the silicon oxide film 7 are removed from the peripheral circuitry.

Abstract: An isolation oxide film whose upper surface is higher than a surface of a substrate is formed in the substrate. A silicon oxide film is formed on the substrate between the isolation oxide films. A self-aligned polysilicon film is formed on the silicon oxide film between the isolation oxide films. After forming a resist pattern covering the peripheral circuitry, the isolation oxide films in the memory cell are etched by a predetermined thickness. An ONO film is formed on the entire surface of the substrate, a second resist pattern covering the memory cell is formed. Then, the ONO film, the polysilicon film 8 and the silicon oxide film 7 are removed from the peripheral circuitry.

Abstract: An isolation oxide film whose upper surface is higher than a surface of a substrate is formed in the substrate. A silicon oxide film is formed on the substrate between the isolation oxide films. A self-aligned polysilicon film is formed on the silicon oxide film between the isolation oxide films. After forming a resist pattern covering the peripheral circuitry, the isolation oxide films in the memory cell are etched by a predetermined thickness. An ONO film is formed on the entire surface of the substrate, a second resist pattern covering the memory cell is formed. Then, the ONO film, the polysilicon film 8 and the silicon oxide film 7 are removed from the peripheral circuitry.

Abstract: An isolation oxide film whose upper surface is higher than a surface of a substrate is formed in the substrate. A silicon oxide film is formed on the substrate between the isolation oxide films. A self-aligned polysilicon film is formed on the silicon oxide film between the isolation oxide films. After forming a resist pattern covering the peripheral circuitry, the isolation oxide films in the memory cell are etched by a predetermined thickness. An ONO film is formed on the entire surface of the substrate, a second resist pattern covering the memory cell is formed. Then, the ONO film, the polysilicon film 8 and the silicon oxide film 7 are removed from the peripheral circuitry.

Abstract: A semiconductor device ensuring an isolation of elements by a trench is provided. A method of manufacturing the semiconductor device includes the step of forming a silicon nitride film having an aperture, the step of selectively removing a part of a silicon substrate along aperture to form a recess defined by a side surface and a bottom surface in silicon substrate, the step of oxidizing the side surface and the bottom surface of the recess to form a thermal oxide film having a side portion and a bottom portion, and the step of selectively removing bottom portion of thermal oxide film and a part of silicon substrate by using silicon nitride film as a mask to form a trench.

Abstract: A semiconductor manufacturing method is mainly contemplated, improved to prevent an altered surface layer of a resist from being removed when a single patterned resist is used to provide dry-etch and wet-etch successively. On a semiconductor substrate an insulation film and a conductive layer are formed successively. On the conductive layer a patterned resist is formed. With the patterned resist used as a mask, the conductive layer is dry-etched. A surface layer of the patterned resist is partially removed. With the patterned resist used as a mask, the insulation film is wet-etched.

Abstract: A nonvolatile semiconductor memory device that can be miniaturized is provided. A method of manufacturing the nonvolatile semiconductor memory device includes the steps of: forming an interlayer insulating film covering a stacked structure and a sidewall insulating film and having a top surface approximately parallel to a main surface; forming a resist pattern as a mask layer on the top surface of the interlayer insulating film; forming a groove as an opening in the interlayer insulating film to be positioned between the sidewall insulating films formed at the adjacent stacked structures; and forming a source region extending along a plurality of floating gate electrodes by implanting impurity ions from the groove to the main surface.

Abstract: A nonvolatile semiconductor memory device that can be miniaturized is provided. A method of manufacturing the nonvolatile semiconductor memory device includes the steps of: forming an interlayer insulating film covering a stacked structure and a sidewall insulating film and having a top surface approximately parallel to a main surface; forming a resist pattern as a mask layer on the top surface of the interlayer insulating film; forming a groove as an opening in the interlayer insulating film to be positioned between the sidewall insulating films formed at the adjacent stacked structures; and forming a source region extending along a plurality of floating gate electrodes by implanting impurity ions from the groove to the main surface.

Abstract: A nonvolatile semiconductor memory device including a semiconductor substrate 1, a plurality of memory cells 1a on the semiconductor substrate including transistors having floating gate electrodes and control gate electrodes. Source lines 30 are formed in a self-alignment manner with respect to a control gate electrodes. The surface of the semiconductor substrate 1 has such a periodical unevenness along the source lines 30 which has a diffusion layer 30a that an impurity is distributed along the surface of the semiconductor substrate 1 and a buried diffusion layer 30b that an impurity is distributed at a position deeper than said diffusion layer 30a. The buried diffusion layer 30b connects a plurality of portions of the diffusion layers 30a under the bottom surface 5b of the recess portion 5 to each other.

Abstract: A semiconductor device is provided which is capable of reducing the number of masking processes in forming contact holes. The semiconductor device comprises a semiconductor substrate (1), a gate structure (9), a stopper film (11), an interlayer insulation film (12), a contact hole (17) extending from the upper surface (13) of the interlayer insulation film (12) to the semiconductor substrate (1), a metal material (18) buried in the contact hole (17), a first metal wiring layer (19), an interlayer insulation film (20), a contact hole (23) extending from the upper surface (21) of the interlayer insulation film (20) to the first metal wiring layer (19), and a contact hole (24) extending from the upper surface (21) of the interlayer insulation film (20) to a gate electrode (7) of the gate structure (9). The contact hole (24) is formed at the same time as the contact hole (23).

Abstract: Binary mode memory cells each storing data of a single bit per cell and multilevel mode memory cells each storing data of multi bits per cell are allocated with different address regions in a fixed manner and are formed in different regions. According to the fixed address allocation, the binary mode memory cells and the multilevel mode memory cells can be optimized individually and separately. In this way, the reliability of a nonvolatile semiconductor memory device is improved and the area occupied by the memory arrays is reduced.

Abstract: A highly reliable semiconductor device capable of preventing generation of a leakage current is provided. The semiconductor device comprises a silicon substrate having a main surface and including a trench formed on the main surface. The trench is defined by surfaces including a bottom surface, a side surface, continuous to the bottom surface, having first inclination with respect to the main surface, and an intermediate surface, formed between the main surface and the bottom surface, having second inclination smaller than the first inclination with respect to the main surface. The semiconductor device further comprises an n-type impurity region.