Patents by Inventor Shuangxi Li

Shuangxi Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11894966
    Abstract: The present disclosure provides a method for estimating a frequency offset, including: extracting sampling points from an input signal according to preset intervals to obtain a plurality of groups of sampling points, with the preset intervals of the groups of sampling points being different; performing processes on a current sampling point and the groups of sampling points to obtain data of arguments of complex numbers corresponding to the preset intervals; and determining an estimation value of a frequency offset of a current input signal according to the data of arguments of complex numbers corresponding to the preset intervals. The present disclosure further provides an apparatus for estimating a frequency offset, an electronic device and a computer-readable medium.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: February 6, 2024
    Assignee: SANECHIPS TECHNOLOGY CO., LTD.
    Inventors: Shuangxi Li, Yangzhong Yao, Nanshan Cao, Yunpeng Li
  • Publication number: 20230144980
    Abstract: The present disclosure provides a method for estimating a frequency offset, including: extracting sampling points from an input signal according to preset intervals to obtain a plurality of groups of sampling points, with the preset intervals of the groups of sampling points being different; performing processes on a current sampling point and the groups of sampling points to obtain data of arguments of complex numbers corresponding to the preset intervals; and determining an estimation value of a frequency offset of a current input signal according to the data of arguments of complex numbers corresponding to the preset intervals. The present disclosure further provides an apparatus for estimating a frequency offset, an electronic device and a computer-readable medium.
    Type: Application
    Filed: April 2, 2021
    Publication date: May 11, 2023
    Inventors: Shuangxi LI, Yangzhong YAO, Nanshan CAO, Yunpeng LI
  • Publication number: 20220389067
    Abstract: Methods of treating subjects having G4C2 dipeptide repeat expansion in the gene C9ORF72, including subjects having amyotrophic lateral sclerosis or frontotemporal degeneration (ALS/FTD), are provided. Compounds directed at reducing the toxicity of G4C2 dipeptide repeat expansion in the gene C9ORF72 are described.
    Type: Application
    Filed: November 5, 2020
    Publication date: December 8, 2022
    Applicant: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Bingwei Lu, Zhihao Wu, Shuangxi Li
  • Patent number: 8661308
    Abstract: The present invention discloses a method for fast cyclic redundancy check (CRC) encoding, and includes: mapping a CRC encoding generator polynomial to generate an (r+1)-order transfer matrix J; deleting a first row and a first column of said (r+1)-order transfer matrix J to obtain an r-order transfer matrix; forming a r×1 column matrix by first columns of 2nd to r+1th rows of said (r+1)-order transfer matrix; obtaining a zero input transfer matrix and a zero state transfer matrix of CRC encoding by the r-order transfer matrix and the r×1 column matrix; adding dummy bits before an input bit stream; and obtaining a CRC encoding check sequence according to the zero input transfer matrix, the zero state transfer matrix and the input bit stream after adding the dummy bits. The present invention further discloses an apparatus for fast cyclic redundancy check encoding.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: February 25, 2014
    Assignee: ZTE Corporation
    Inventor: Shuangxi Li
  • Publication number: 20120102382
    Abstract: The present invention discloses a method for fast cyclic redundancy check (CRC) encoding, and includes: mapping a CRC encoding generator polynomial to generate an (r+1)-order transfer matrix J; deleting a first row and a first column of said (r+1)-order transfer matrix J to obtain an r-order transfer matrix; forming a r×1 column matrix by first columns of 2nd to r+1th rows of said (r+1)-order transfer matrix; obtaining a zero input transfer matrix and a zero state transfer matrix of CRC encoding by the r-order transfer matrix and the r×1 column matrix; adding dummy bits before an input bit stream; and obtaining a CRC encoding check sequence according to the zero input transfer matrix, the zero state transfer matrix and the input bit stream after adding the dummy bits. The present invention further discloses an apparatus for fast cyclic redundancy check encoding.
    Type: Application
    Filed: April 23, 2010
    Publication date: April 26, 2012
    Applicant: ZTE CORPORATION
    Inventor: Shuangxi Li