Abstract: Improving performance in solid state devices (SSDs) by controlling or throttling the depth of the request queue. In one implementation, a method includes monitoring a request queue in a solid state device (an SSD), the request queue comprising a first request and a second request having an actual time interval therebetween, determining a number of active memory dies of the SSD, determining a target interval based on the number of active memory dies and a target number of active memory dies, and responsive to the actual time interval being less than the target interval, delaying acting on the second request until after the target interval.

Abstract: Hard errors are determined for an unsuccessful decoding of codeword bits read from NAND memory cells via a read channel and input to a low-density parity check (LDPC) decoder. A bit error rate (BER) for the hard errors is estimated and BER for the read channel is estimated. Hard error regions are found using a single level cell (SLC) reading of the NAND memory cells. A log likelihood ratio (LLR) mapping of the codeword bits input to the LDPC decoder is changed based on the hard error regions, the hard error BER, and/or the read channel BER.

Abstract: Improving performance in solid state devices (SSDs) by controlling or throttling the depth of the request queue. In one implementation, a method includes monitoring a request queue in a solid state device (an SSD), the request queue comprising a first request and a second request having an actual time interval therebetween, determining a number of active memory dies of the SSD, determining a target interval based on the number of active memory dies and a target number of active memory dies, and responsive to the actual time interval being less than the target interval, delaying acting on the second request until after the target interval.

Abstract: Hard errors are determined for an unsuccessful decoding of codeword bits read from NAND memory cells via a read channel and input to a low-density parity check (LDPC) decoder. A bit error rate (BER) for the hard errors is estimated and BER for the read channel is estimated. Hard error regions are found using a single level cell (SLC) reading of the NAND memory cells. A log likelihood ratio (LLR) mapping of the codeword bits input to the LDPC decoder is changed based on the hard error regions, the hard error BER, and/or the read channel BER.

Abstract: Improving performance in solid state devices (SSDs) by controlling or throttling the depth of the request queue. In one implementation, a method includes monitoring a request queue in a solid state device (an SSD), the request queue comprising a first request and a second request having an actual time interval therebetween, determining a number of active memory dies of the SSD, determining a target interval based on the number of active memory dies and a target number of active memory dies, and responsive to the actual time interval being less than the target interval, delaying acting on the second request until after the target interval.

Abstract: Improving performance in solid state devices (SSDs) by controlling or throttling the depth of the request queue. In one implementation, a method includes monitoring a request queue in a solid state device (an SSD), the request queue comprising a first request and a second request having an actual time interval therebetween, determining a queue depth for the request queue, determining a target interval based on the queue depth and a target queue depth, and responsive to the actual time interval being less than the target interval, delaying acting on the second request until after the target interval.

Abstract: Improving performance in solid state devices (SSDs) by controlling or throttling the depth of the request queue. In one implementation, a method includes monitoring a request queue in a solid state device (an SSD), the request queue comprising a first request and a second request having an actual time interval therebetween, determining a number of active memory dies of the SSD, determining a target interval based on the number of active memory dies and a target number of active memory dies, and responsive to the actual time interval being less than the target interval, delaying acting on the second request until after the target interval.

Abstract: Improving performance in solid state devices (SSDs) by controlling or throttling the depth of the request queue. In one implementation, a method includes monitoring a request queue in a solid state device (an SSD), the request queue comprising a first request and a second request having an actual time interval therebetween, determining a queue depth for the request queue, determining a target interval based on the queue depth and a target queue depth, and responsive to the actual time interval being less than the target interval, delaying acting on the second request until after the target interval.

Abstract: Improving performance in solid state devices (SSDs) by controlling or throttling an interval between requests. In one implementation, a method includes monitoring a request queue in a solid state device (an SSD), the request queue comprising a first request and a second request having an actual time interval therebetween, and responsive to the time interval being less than a target interval, delaying acting on the second request until after the target interval.

Abstract: Hard errors are determined for an unsuccessful decoding of codeword bits read from NAND memory cells via a read channel and input to a low-density parity check (LDPC) decoder. A bit error rate (BER) for the hard errors is estimated and BER for the read channel is estimated. Hard error regions are found using a single level cell (SLC) reading of the NAND memory cells. A log likelihood ratio (LLR) mapping of the codeword bits input to the LDPC decoder is changed based on the hard error regions, the hard error BER, and/or the read channel BER.

Abstract: A method includes programming data in a block of a storage device, and reading back the programmed data and determining a maximum error count for the block. A code rate index that satisfies correction of the maximum error count for the block is determined. A current code rate index is adjusted to the code rate index that satisfies correction of the maximum error count for the block.

Abstract: A method includes determining a portion of a block of a storage device to read after programming, and reading the portion of the block and determining a maximum error count for the portion of the block. The maximum error count is compared to a threshold. When the maximum error count exceeds the threshold, a code rate of an error correction coding used to program the block is adjusted, or a code rate test is performed on the entire block.

Abstract: A method includes determining a portion of a block of a storage device to read after programming, and reading the portion of the block and determining a maximum error count for the portion of the block. The maximum error count is compared to a threshold. When the maximum error count exceeds the threshold, a code rate of an error correction coding used to program the block is adjusted, or a code rate test is performed on the entire block.

Abstract: A method includes programming data in a block of a storage device, and reading back the programmed data and determining a maximum error count for the block. A code rate index that satisfies correction of the maximum error count for the block is determined. A current code rate index is adjusted to the code rate index that satisfies correction of the maximum error count for the block.

Abstract: A semiconductor storage device includes at least one memory from among a primary memory, a mirror memory storing data corresponding to data stored in the primary memory, and a buffer memory; and a controller that controls the at least one memory so as to store data in the at least one memory and read data from the at least one memory.

Abstract: A semiconductor storage device includes at least one memory from among a primary memory, a minor memory storing data corresponding to data stored in the primary memory, and a buffer memory; and a controller that controls the at least one memory so as to store data in the at least one memory and read data from the at least one memory.

Abstract: A memory controller sets an estimated cell error ratio CERest based on an estimated retention time Tret obtained from a calculated bit error ratio BER, a number of rewrite times NW/E, data Datatag of a target cell and data Dataadj of memory cells surrounding the target cell, sets an upper-level page LLRu and a lower-level page LLRl with regard to all bits of read-out one-page data using the set estimated cell error ratio CERest and performs error correction and decoding of data read out from a flash memory using the settings of the upper-level page LLRu and the lower-level page LLRl. This improves the error correction capability, while suppressing an increase in processing time.

Abstract: When detected number of errors data Nerror exceeds the upper limit number of errors Nmax, an error correction circuit of a memory controller stores twice as long data length as stored data length for execution Sdata as the data length for execution Sdata in a correction information memory unit, and code length Scref longer than the data length for execution Sdata and detectable more errors than the upper limit number of errors as the code length for execution Scode in the correction information memory unit 32 (step S100 and S110). The error correction circuit encodes input data using BCH code having the stored code length for execution Scode, stored encoded data in a semiconductor memory device, is input data stored in the semiconductor memory device, performs error correction for input data using BCH code, and decode error corrected data.

Abstract: Voltages are applied to supply voltage application points of memory cells of an SRAM, a semiconductor substrate, a word line and bit lines so that voltage Vdd takes value V1, substrate voltage Vsub becomes 0 V, word line voltage Vw1 takes value V1, bit line voltage Vbll becomes 0 V, and bit line voltage Vblr takes value V1, the voltage difference between the word line and one of the bit lines is forced to be equal to a voltage difference V1h higher than a normal voltage difference V1 and the voltage difference between the word line and the other bit line is forced to be equal the normal voltage difference V1 lower than the voltage V1h to inject electrons into an insulating layer near a diffusion layer connected to an output terminal of an inverter constituting the memory cell. This can improve the operating characteristics of the memory cell.

Abstract: When detected number of errors data Nerror exceeds the upper limit number of errors Nmax, an error correction circuit of a memory controller stores twice as long data length as stored data length for execution Sdata as the data length for execution Sdata in a correction information memory unit, and code length Scref longer than the data length for execution Sdata and detectable more errors than the upper limit number of errors as the code length for execution Scode in the correction information memory unit 32 (step S100 and S110). The error correction circuit encodes input data using BCH code having the stored code length for execution Scode, stored encoded data in a semiconductor memory device, is input data stored in the semiconductor memory device, performs error correction for input data using BCH code, and decode error corrected data.