Abstract: A caching system, having a first instruction cache and second instruction cache, receives an instruction address from an instruction fetch unit. For an address resulting in a cache miss in both first cache and second cache, an instruction associated with the address is retrieved from computer memory and stored with the address in first cache. For an address resulting in a cache miss in second cache and a cache hit in first cache, the instruction associated with the address is retrieved from first cache. If no instruction in second cache matches the retrieved instruction, the retrieved instruction is stored in second cache and associated with the received address; otherwise the matching instruction is associated with the received address. For an address resulting in a cache hit in second cache, the instruction associated with the address is retrieved from second cache. The retrieved instruction is returned to the instruction fetch unit.

Abstract: Storage system that includes: an address search section for i) storing an address for frequent use data and a data index assigned to the address, ii) acquiring an address of write or read data, and iii) searching stored addresses with the acquired address, a frequent use data storage section for i) storing a tag related to the use data and the index, ii) acquiring the index when an address acquired by the search section has hit a stored address, and iii) identifying frequent use data that corresponds to the tag, a data comparator for i) acquiring the frequent use data from the storage section, ii) comparing the data with write data, and iii) identifying frequent use data that hit the write data, and an compression-expansion section for acquiring and compressing the write data and the frequent use data from the comparator, and for acquiring the read data.

Abstract: An apparatus that controls access by multiple IP cores to a bus is provided. The apparatus includes a main controller and multiple sub controllers, each of the sub controllers being associated with each IP cores. The main controller switches connection between each of the IP cores and the bus according to a schedule predetermined based on predetermined time slices. Each of the sub controllers controls access by the IP core to the bus according to a schedule under the control of the main controller. Embodiments of the present invention provide method and apparatus to ensure real-time accessibility to a bus shared by multiple IP cores and improve bus use efficiency.

Abstract: To virtualize a system without having to incorporate a special mechanism into software and with increases in overhead suppressed, by controlling memory accesses made by processors using hardware. A device controls memory accesses made by processors and includes multiple address tables that correspond to multiple operating systems (OSs) run by the processors and each translate the logical address of the destination of a memory access made by one of the processors into a physical address in a memory or memory; and a table selection unit that, when one of the processors makes a memory access, obtains identification information of the processor and selects an address table corresponding to an OS run by the processor identified by the identification information from among the address tables as an address table that performs address translation with respect to the memory access.

Abstract: An apparatus that controls access by multiple IP cores to a bus is provided. The apparatus includes a main controller and multiple sub controllers, each of the sub controllers being associated with each IP cores. The main controller switches connection between each of the IP cores and the bus according to a schedule predetermined based on predetermined time slices. Each of the sub controllers controls access by the IP core to the bus according to a schedule under the control of the main controller. Embodiments of the present invention provide method and apparatus to ensure real-time accessibility to a bus shared by multiple IP cores and improve bus use efficiency.

Abstract: One object of the present invention is to provide an LSI that can dynamically perform appropriate adjustment for a power voltage to be supplied to an internal circuit, not only at the time of the occurrence of the initial change of a performance due to a variation or variety factors through a manufacturing process, but also at the time of the occurrence of the time elapsed change.

Abstract: The present invention generates an output clock signal CLKreq having a frequency freq between the frequency fref/A of a divided clock signal CKL1 and the frequency fref/(A+1) of a divided clock signal CLK2. A clock divider circuit selectively generates divided clock signals CLK1, CLK2. A discrete value correction circuit controls the clock divider circuit so as to repeat C times the process of generating the clock signal CLK2 once and the clock signal CLK1 (Q?1) times and then to generate the clock signal CLK1 R times if C<D and so as to repeat D times the process of generating the clock signal CLK1 once and the clock signal CLK2 (Q?1) times and then to generate the clock signal CLK2 R times if C>D. A, B, and C are natural numbers satisfying freq=fref/(A+C/B). In D=B?C, Q is a quotient of B/C if C<D or a quotient of B/D if C>D.

Abstract: A mixed architecture system on chip is provided by combining a CoreConnect system on chip architecture with an AMBA system on chip architecture. To eliminate data transfer and bus error that could occur in the mixed architecture, an additional peripheral bus and bridge are provided to manage communication with AHB resources.

Abstract: One object of the present invention is to provide an LSI that can dynamically perform appropriate adjustment for a power voltage to be supplied to an internal circuit, not only at the time of the occurrence of the initial change of a performance due to a variation or variety factors through a manufacturing process, but also at the time of the occurrence of the time elapsed change.

Abstract: One object of the present invention is to provide an LSI that can dynamically perform appropriate adjustment for a power voltage to be supplied to an internal circuit, not only at the time of the occurrence of the initial change of a performance due to a variation or variety factors through a manufacturing process, but also at the time of the occurrence of the time elapsed change.

Abstract: A mixed architecture system on chip is provided by combining a CoreConnect system on chip architecture with an AMBA system on chip architecture. To eliminate data transfer and bus error that could occur in the mixed architecture, an additional peripheral bus and bridge are provided to manage communication with AHB resources.

Abstract: The present invention generates an output clock signal CLKreq having a frequency freq between the frequency fref/A of a divided clock signal CKL1 and the frequency fref/(A+1) of a divided clock signal CLK2. A clock divider circuit selectively generates divided clock signals CLK1, CLK2. A discrete value correction circuit controls the clock divider circuit so as to repeat C times the process of generating the clock signal CLK2 once and the clock signal CLK1 (Q?1) times and then to generate the clock signal CLK1 R times if C<D and so as to repeat D times the process of generating the clock signal CLK1 once and the clock signal CLK2 (Q?1) times and then to generate the clock signal CLK2 R times if C>D. A, B, and C are natural numbers satisfying freq=fref/(A+C/B). In D=B?C, Q is a quotient of B/C if C<D or a quotient of B/D if C>D.