Patents by Inventor Shuichi Tahara

Shuichi Tahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170262044
    Abstract: An information processing apparatus according to the present invention includes: a detection unit that detects detection information that is information indicating an external state of the apparatus; a communication unit that receives reception information that is a determination result given by another apparatus; and a control unit that calculates a first determination result that is a result acquired by determining a state of a surrounding of the apparatus based on the detection information and the reception information, transmits the first determination result to the another apparatus via the communication unit, and activates a necessary function for the detection unit or the communication unit and stops an unnecessary function thereof.
    Type: Application
    Filed: September 7, 2015
    Publication date: September 14, 2017
    Applicant: NEC Corporation
    Inventors: Takashi TAKENAKA, Shuichi TAHARA, Kenichi OYAMA, Nobuharu KAMI, Hiroto SUGAHARA, Noboru SAKIMURA, Kosuke NISHIHARA, Naoki KASAI
  • Patent number: 7948783
    Abstract: An MRAM comprises: a plurality of magnetic memory cells each having a magnetoresistive element; and a magnetic field application section. The magnetic field application section applies an offset adjustment magnetic field in a certain direction to the plurality of magnetic memory cells from outside the plurality of magnetic memory cells. Respective data stored in the plurality of magnetic memory cells become the same when the offset adjustment magnetic field is removed.
    Type: Grant
    Filed: November 12, 2007
    Date of Patent: May 24, 2011
    Assignee: NEC Corporation
    Inventors: Tadahiko Sugibayashi, Takeshi Honda, Noboru Sakimura, Nobuyuki Ishiwata, Shuichi Tahara
  • Publication number: 20100046284
    Abstract: An MRAM comprises: a plurality of magnetic memory cells each having a magnetoresistive element; and a magnetic field application section. The magnetic field application section applies an offset adjustment magnetic field in a certain direction to the plurality of magnetic memory cells from outside the plurality of magnetic memory cells. Respective data stored in the plurality of magnetic memory cells become the same when the offset adjustment magnetic field is removed.
    Type: Application
    Filed: November 12, 2007
    Publication date: February 25, 2010
    Inventors: Tadahiko Sugibayshi, Takeshi Honda, Noboru Sakimura, Nobuyuki Ishiwata, Shuichi Tahara
  • Patent number: 6320369
    Abstract: A superconducting current measuring circuit is provided with a detection loop through which a current flows by the influence of a magnetic field generated by a measurement target current. The detection loop contains a superconductor. The superconducting current measuring circuit is also provided with a superconducting sampler circuit for measuring the current flowing through the detection loop.
    Type: Grant
    Filed: October 6, 1999
    Date of Patent: November 20, 2001
    Assignee: NEC Corporation
    Inventors: Mutsuo Hidaka, Shuichi Tahara
  • Patent number: 4603263
    Abstract: A Josephson pulse generator of the current injection type is composed of a first group of N (N.gtoreq.2) resistors, one end of each being connected together, the other ends of two of the N resistors being connected to first and second nodes. A second group of serially connected N-1 resistors is connected between the first and second nodes and to the other ends of the N-2 resistors in the first group not connected to the first and second nodes. N Josephson junctions are each connected between a reference potential and the other end of a different one of the N resistors. Two additional Josephson junctions, each having one end thereof connected, respectively, to the first node and the second node is provided along with an additional resistor connected between the other end of the Josephson junction connected to the first node and the reference potential.
    Type: Grant
    Filed: February 23, 1983
    Date of Patent: July 29, 1986
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Shuichi Tahara, Jun'ichi Sone