Abstract: In order to overcome the problem that conditionally executed instructions are executed as no-operation instructions if their condition is not fulfilled, leading to poor utilization efficiency of the hardware and lowering the effective performance, the processor decodes a number of instructions that is greater than the number of provided computing units and judges their execution conditions with an instruction issue control portion before the execution stage, Instructions for which the condition is false are invalidated, and subsequent valid instructions are assigned so that the computing units (hardware) is used efficiently. A compiler performs scheduling such that the number of instructions whose execution condition is true does not exceed the upper limit of the degree of parallelism of the hardware. The number of instructions arranged in parallel at each cycle may exceed the degree of parallelism of the hardware.

Abstract: A compiler device includes a conditional-executable-instruction generation unit and a branch instruction insertion unit. The conditional-executable-instruction generation unit generates a conditional executable instruction that is executed when a condition that the conditional executable instruction refers to is satisfied. In the case where there is a section containing a non-executive condition under which no instruction is executed in one cycle or a plurality of cycles in series, the branch instruction insertion unit inserts a conditional branch instruction that refers to the non-executive condition and instructs to branch to a cycle immediately after a last cycle of the section, to after an instruction of a cycle immediately before a start of the section.

Abstract: When a branch instruction is decoded by the instruction decoders 409a-409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

Abstract: An optimization apparatus is capable of improving the execution efficiency of a loop that includes a loop carry dependency between consecutive iterations of the loop. For example, a value resulting from one iteration is used in an immediately following iteration. When the arithmetic expression “a[i+1]=a[i]*3+2;” is included in a loop body, and a value resulting from the arithmetic expression “a[i+1]=a[i]*3+2;” in one iteration is used in a following iteration, execution delays occur in pipeline processing of the loop. Here, the arithmetic expression “a[i+1]=a[i]*3+2;” is transformed into the arithmetic expression “a[i+4]=a[i]*81+80;” to expand the dependency distance. By doing so, the execution delays can be decreased.

Abstract: When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

Abstract: When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

Abstract: A compound device has the structural hardware of a digital television, is connected to an antenna and a telephone station, and by reading out and running either a digital television (DTV) program or a base station program with a general processor, it has both the function of a digital television and the function of a portable telephone base station. The owner of the compound device receives discounts in their subscribed telephone fee or their power fee based on records in a communication record portion. Thus, a compound device in which a digital television is given the function of a portable telephone base station is provided, so that a novel infrastructure can be achieved in which insufficiencies in base stations are made up for without requiring equipment investment expenditures and portable device owners are given financial benefits in compensation for allowing the public use of their private possession as a portable telephone base station.

Abstract: A processor which decodes and executes an instruction sequence includes: a state hold unit for holding, when a predetermined instruction is executed, a renewal state for an execution result of the predetermined instruction; an obtaining unit for obtaining an instruction sequence composed of instructions matching instructions assigned to an instruction set of the processor, where the instruction set is assigned first conditional instructions, a first state condition for a first conditional instruction being mutually exclusive with a second state condition for a second conditional instruction which has a same operation code as the first conditional instruction, the instruction set not being assigned the second conditional instruction, and the first state condition and the second state condition specifying either of one state and a plurality of states; a decoding unit for decoding each instruction in the obtained instruction sequence one by one; a judging unit for judging whether the renewal state is included in

Abstract: When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

Abstract: A program generation apparatus according to the present invention includes a translation unit and a generation unit. The translation unit accepts a single HLSL (high level scripting language) script that defines a variety of program structures for programs to be generated, and translates the HLSL script into a plurality of MLSL (middle level scripting language) scripts, each of which describes one of the plurality of program structures defined by the HLSL script, which are different from each other. The generation unit generates programs that respectively correspond to the plurality of MLSL scripts.

Abstract: A test program generating apparatus for a compiler comprising: a conditional expression generating unit operable to receive a description of a control structure of a program and generate a plurality of conditional expressions to be inserted into insert parts of the conditional expressions of the control structure using a linear programming method, the plurality of conditional expressions allowing a control flow of the program to pass through all paths in the control structure; an initial value generating unit operable to generate initial values of variables, for each of all the paths, which are included in the plurality of conditional expressions for allowing the control flow of the program to pass through all the paths in the control structure; and a test program generating unit operable to generate a test program based on the control structure, the conditional expressions and the initial values.

Abstract: A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code “cc” that indicates a branch operation which uses a stored value of the implicitly indicated constant register 36 as the branch address, or (2) a constant “const”. The content of the 4-bit operation field 52 is specified by a format code provided in the format field 51.

Abstract: An SZ (size information) section is provided for each of registers that make up a register file. Suppose an instruction decoded requests that operand data of a particular size be loaded from a RAM into the register file or that immediate operand data of a particular size be transferred to the register file. Then, the size information of the operand data will be retained in the SZ section. The instruction decoded may also be an arithmetic and logical operation instruction requesting that operand data in the register file be referred to or an instruction requesting that the operand data be stored from the register file into the RAM. In such a case, the size information will be read out from the SZ section of the register file and only parts of various components constituting manipulation means (like ALU), which have been specified by the size information, will be enabled. As a result, the power, which is usually dissipated by a processor handling data of multiple sizes, can be cut down effectively.

Abstract: Disclosed is a compiler apparatus for generating an instruction code composed of instruction sets each including an instruction that designates an m-bit immediate value indicating a location of a data item in a memory area. The compiler apparatus sequentially selects, based on one data attribute, a data item from a group X composed of a plurality of data items; and judges, each time a data item is selected, whether the selected data item is allocatable to an n-byte memory area (n≦2m). When the judgment is negative, the compiler apparatus specifies, based on a different data attribute, a data item out of all the selected data items and exclude the specified data item from the group X, and repeats the selection until all the data items remaining in the group X after excluding all the specified data items are judged to be allocatable to the memory area.

Abstract: The present invention provides a highly-flexible compiler that a user can control optimization by the compiler precisely.

Abstract: A dependency analysis unit creates a dependency graph showing dependencies between instructions acquired from an assembler code generation unit. A precedence constraint rank calculation unit assigns predetermined weights to arcs in the graph, and adds up weights to calculate a precedence constraint rank of each instruction. When a predecessor and a successor having a dependency and an equal precedence constraint rank cannot be processed in parallel due to a resource constraint, a resource constraint evaluation unit raises the precedence constraint rank of the predecessor. A priority calculation unit sets the raised precedence constraint rank as a priority of the predecessor. An instruction selection unit selects an instruction having a highest priority. An execution timing decision unit places the selected instruction in a clock cycle. The selection by the instruction selection unit and the placement by the execution timing decision unit are repeated until all instructions are placed in clock cycles.

Abstract: A program conversion apparatus including a machine-language storage unit and a conversion unit. The machine-language storage unit stores sets of two or more types of machine-language codes which correspond to components of a predetermined type included in instructions of a source program. The two or more types of machine-language codes in each set have different bit patterns. The conversion unit converts the instructions of the source program into the machine-language instructions. In this conversion, the conversion means converts each predetermined-type component selectively into one of the two or more types of machine-language codes so that the converted machine-language instructions have less digit-bit changes.

Abstract: Nanopatterned devices are easily fabricated, over large surface areas when desired, by forming a multilayer article of deformable substrate, brittle layer, and coating layer, and deforming the multilayer film such that a plurality of cracks are formed therein. The cracks have different physicochemical properties than the non-cracked coating layer, and advantageously serve as attachment points for culturing microorganisms.

Abstract: The first, second, and third operating units 441 to 443 each perform a predetermined operation according to an instruction before a point of time partway through a clock cycle. When having performed a comparison operation, each operating unit outputs a result value to the condition flag operating unit 51. The condition flag operating unit 51 calculates a new condition flag value by performing a logical operation on either (a) a value that has been read from the condition flag register 46 and the result value or (b) the result values themselves. The condition flag operating unit 51 outputs, before the clock cycle ends, the new condition flag value to one of the first, second, and third gates 451 to 453 that is related to a conditional instruction so as to control nullification of the conditional instruction. The condition flag register 46 stores therein the new condition flag value.

Abstract: The present invention is directed, in certain embodiments, to improved, small scale systems and methods able to selectively treat parts of a single cell, including, in certain embodiments, portions of a main body portion of a single cell, and able, in certain embodiments, to establish long-term gradients of active substances within subcellular regions of a single cell. The present invention provides, in some embodiments, techniques for selectively contacting a portion of the surface of a biological cell with a fluid or fluid component carrying a particular potential for a biophysical or biochemical interaction with the cell, and simultaneously contacting a different portion of the surface of the cell with another fluid or fluid component having a different potential for the biophysical or biochemical interaction with the cell.