Abstract: A circuit design assisting device for assisting design of a circuit, the circuit design assisting device includes a storage unit that stores circuit connection data of the circuit, a selecting unit that chooses a storage element that holds a signal inputted from an input terminal based on a clock signal and outputs the signal from an output terminal from the circuit connection data, a tracing unit that traces a logical connection from the input terminal of the chosen storage element in an opposite direction against propagation of the signal based on the circuit connection data, and a control unit that suspends the tracing unit to trace the logical connection when the tracing unit reaches to an element having two or more input terminals.

Abstract: A buffer device that transfers data and is shared by a plurality of CPU cores arranged in a symmetrically inverted manner about a predetermined reference line, each CPU core breaking up a data block into a plurality of data lines and outputting the data lines via a plurality of ports, includes a plurality of line buffers that correspond to the data lines and are connected to the ports in the CPU cores, wherein the line buffers are paired into line buffer groups, and the line buffers in each buffer group are arranged symmetrically about the reference line.

Abstract: A cache memory control unit that controls a cache memory comprises: a PF-PORT 22 and MI-PORT 21 that receive a prefetch request and demand fetch request issued from a primary cache; and a processing pipeline 27 that performs swap processing when the MI-PORT 21 receives a demand fetch request designating the same memory address as that designated by a prefetch request that has already been received by the PF-PORT 22, the swap processing being performed so that an MIB 28 that has been ensured for replying the prefetch request is used for a reply to the demand fetch request following the prefetch request.

Abstract: A buffer device that transfers data and is shared by a plurality of CPU cores arranged in a symmetrically inverted manner about a predetermined reference line, each CPU core breaking up a data block into a plurality of data lines and outputting the data lines via a plurality of ports, includes a plurality of line buffers that correspond to the data lines and are connected to the ports in the CPU cores, wherein the line buffers are paired into line buffer groups, and the line buffers in each buffer group are arranged symmetrically about the reference line.

Abstract: A cache memory device in an N-way (N is an integer of 2 or larger) set associative system includes a way detection unit detecting one way exhibiting a specified strength on the basis of a reference history defined as bits representing a win/loss relation between ways and updated so as to indicate one way exhibiting the specified strength, and an error detection unit detecting a bit error in the reference history if the way detection unit does not detect one way exhibiting the specified strength.

Abstract: A cache memory control unit that controls a cache memory comprises: a PF-PORT 22 and MI-PORT 21 that receive a prefetch request and demand fetch request issued from a primary cache; and a processing pipeline 27 that performs swap processing when the MI-PORT 21 receives a demand fetch request designating the same memory address as that designated by a prefetch request that has already been received by the PF-PORT 22, the swap processing being performed so that an MIB 28 that has been ensured for replying the prefetch request is used for a reply to the demand fetch request following the prefetch request.

Abstract: A cache memory device in an N-way (N is an integer of 2 or larger) set associative system includes a way detection unit detecting one way exhibiting a specified strength on the basis of a reference history defined as bits representing a win/loss relation between ways and updated so as to indicate one way exhibiting the specified strength, and an error detection unit detecting a bit error in the reference history if the way detection unit does not detect one way exhibiting the specified strength.