Patents by Inventor Shuji Katsui

Shuji Katsui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8012858
    Abstract: A method of fabricating a semiconductor device according to one embodiment includes: removing a native oxide film and adhering silicon nitrides on an area of a Si based substrate in hydrogen gas atmosphere under a condition in which a pressure is a first pressure and a temperature is a first temperature, a silicon nitride-containing member being formed on the Si based substrate, the area being a area not covered by the member; lowering the temperature to a second temperature from the first temperature while maintaining the pressure at the first pressure in hydrogen gas atmosphere; lowering the pressure to a second pressure from the first pressure while maintaining the temperature at the second temperature in hydrogen gas atmosphere; and epitaxially growing a crystal on the area of the Si based substrate in a precursor gas atmosphere after the pressure is lowered to the second pressure, the crystal including at least one of Si and Ge, the precursor gas atmosphere including at least one of hydrogen, Si and Ge.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: September 6, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Murano, Ichiro Mizushima, Tsutomu Sato, Shinji Mori, Shuji Katsui, Hiroshi Itokawa
  • Publication number: 20100099241
    Abstract: A method of fabricating a semiconductor device according to one embodiment includes: removing a native oxide film and adhering silicon nitrides on an area of a Si based substrate in hydrogen gas atmosphere under a condition in which a pressure is a first pressure and a temperature is a first temperature, a silicon nitride-containing member being formed on the Si based substrate, the area being a area not covered by the member; lowering the temperature to a second temperature from the first temperature while maintaining the pressure at the first pressure in hydrogen gas atmosphere; lowering the pressure to a second pressure from the first pressure while maintaining the temperature at the second temperature in hydrogen gas atmosphere; and epitaxially growing a crystal on the area of the Si based substrate in a precursor gas atmosphere after the pressure is lowered to the second pressure, the crystal including at least one of Si and Ge, the precursor gas atmosphere including at least one of hydrogen, Si and Ge.
    Type: Application
    Filed: September 15, 2009
    Publication date: April 22, 2010
    Inventors: Masahiko MURANO, Ichiro Mizushima, Tsutomu Sato, Shinji Mori, Shuji Katsui, Hiroshi Itokawa
  • Patent number: 6929991
    Abstract: The present invention provides a semiconductor device and a method of manufacturing the same improved in reliability of a gate insulating film by increasing a total charge amount Qbd by suppressing a film stress of a gate electrode formed of a polysilicon film, to a low value. Since the film stress is closely related to a film formation temperature, it is possible to reduce the film stress lower than the conventional case by forming a film at as a high temperature as 640° C. or more. At this time, when the film stress decreases, the total charge amount Qbd regulating dielectric breakdown of the film increases, improving reliability of the gate insulating film. It is therefore possible to set the film stress of the gate electrode at 200 MPA or less in terms of absolute value by forming the gate electrode at 640° C. or more.
    Type: Grant
    Filed: February 11, 2004
    Date of Patent: August 16, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuuichi Mikata, Shuji Katsui, Hiroshi Akahori
  • Publication number: 20040155271
    Abstract: The present invention provides a semiconductor device and a method of manufacturing the same improved in reliability of a gate insulating film by increasing a total charge amount Qbd by suppressing a film stress of a gate electrode formed of a polysilicon film, to a low value. Since the film stress is closely related to a film formation temperature, it is possible to reduce the film stress lower than the conventional case by forming a film at as a high temperature as 640° C. or more. At this time, when the film stress decreases, the total charge amount Qbd regulating dielectric breakdown of the film increases, improving reliability of the gate insulating film. It is therefore possible to set the film stress of the gate electrode at 200 MPA or less in terms of absolute value by forming the gate electrode at 640° C. or more.
    Type: Application
    Filed: February 11, 2004
    Publication date: August 12, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yuuichi Mikata, Shuji Katsui, Hiroshi Akahori
  • Patent number: 6772045
    Abstract: A system for determining dry cleaning timing, includes: a manufacturing apparatus configured to process materials assigned by a sequence of lots; an apparatus controller configured to control the manufacturing apparatus and obtaining operational conditions of the manufacturing apparatus as apparatus information; a lot information input terminal configured to obtain process conditions of one of the lots as lot information; an apparatus information storage unit configured to store the apparatus information from the apparatus controller as an apparatus information database; a lot information storage unit configured to store the lot information from the lot information input terminal as a lot information database; and a cleaning determination unit configured to determine timing to perform a dry cleaning of the manufacturing apparatus based on the apparatus information database and the lot information database.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: August 3, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shuji Katsui, Masayuki Tanaka, Masaki Kamimura, Hiroshi Akahori, Ichiro Mizushima, Takashi Nakao, Akihito Yamamoto, Shigehiko Saida, Yoshitaka Tsunashima, Yuuichi Mikata
  • Patent number: 6713824
    Abstract: The present invention provides a semiconductor device and a method of manufacturing the same improved in reliability of a gate insulating film by increasing a total charge amount Qbd by suppressing a film stress of a gate electrode formed of a polysilicon film, to a low value. Since the film stress is closely related to a film formation temperature, it is possible to reduce the film stress lower than the conventional case by forming a film at as a high temperature as 640° C. or more. At this time, when the film stress decreases, the total charge amount Qbd regulating dielectric breakdown of the film increases, improving reliability of the gate insulating film. It is therefore possible to set the film stress of the gate electrode at 200 MPA or less in terms of absolute value by forming the gate electrode at 640° C. or more.
    Type: Grant
    Filed: December 14, 1999
    Date of Patent: March 30, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuuichi Mikata, Shuji Katsui, Hiroshi Akahori
  • Publication number: 20030139835
    Abstract: A system for determining dry cleaning timing, includes: a manufacturing apparatus configured to process materials assigned by a sequence of lots; an apparatus controller configured to control the manufacturing apparatus and obtaining operational conditions of the manufacturing apparatus as apparatus information; a lot information input terminal configured to obtain process conditions of one of the lots as lot information; an apparatus information storage unit configured to store the apparatus information from the apparatus controller as an apparatus information database; a lot information storage unit configured to store the lot information from the lot information input terminal as a lot information database; and a cleaning determination unit configured to determine timing to perform a dry cleaning of the manufacturing apparatus based on the apparatus information database and the lot information database.
    Type: Application
    Filed: August 30, 2002
    Publication date: July 24, 2003
    Inventors: Shuji Katsui, Masayuki Tanaka, Masaki Kamimura, Hiroshi Akahori, Ichiro Mizushima, Takashi Nakao, Akihito Yamamoto, Shigehiko Saida, Yoshitaka Tsunashima, Yuuichi Mikata
  • Publication number: 20010015174
    Abstract: semiconductor device, including the step of supplying an oxidizing gas and a nitriding gas onto one main surface of a semiconductor substrate while heating the substrate so as to oxynitride the surface region of the substrate, wherein the supplying step is performed such that the gaseous phase above the main surface of the substrate forms a first region having a substantially uniform temperature in a direction perpendicular to the main surface of the substrate and a second region interposed between the first region and the substrate and having a temperature gradient in a direction perpendicular to the main surface of the substrate such that the temperature is elevated toward the substrate, and the distance from the main surface of the substrate to the interface between the first and second regions is set at 9.5 cm or less.
    Type: Application
    Filed: May 7, 2001
    Publication date: August 23, 2001
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuo Saki, Shuji Katsui
  • Patent number: 6251801
    Abstract: Disclosed is a method of manufacturing a semiconductor device, including the step of supplying an oxidizing gas and a nitriding gas onto one main surface of a semiconductor substrate while heating the substrate so as to oxynitride the surface region of the substrate, wherein the supplying step is performed such that the gaseous phase above the main surface of the substrate forms a first region having a substantially uniform temperature in a direction perpendicular to the main surface of the substrate and a second region interposed between the first region and the substrate and having a temperature gradient in a direction perpendicular to the main surface of the substrate such that the temperature is elevated toward the substrate, and the distance from the main surface of the substrate to the interface between the first and second regions is set at 9.5 cm or less.
    Type: Grant
    Filed: October 6, 1999
    Date of Patent: June 26, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuo Saki, Shuji Katsui