Abstract: The present invention provides a system capable of properly controlling the switching of the operation state of each of a plurality of arithmetic processing resources according to an increase or a decrease in an arithmetic processing load. A distributed processing control system 10 includes a load estimation unit 11 that estimates an estimation arithmetic processing load at a first point of time in a future from a reference point of time, and a state control unit 12 that starts the processing for switching the operation state of an arithmetic processing resource Sj so as to satisfy a first condition, in which the estimated arithmetic processing load is included in a predetermined range of an estimation processing capacity of the arithmetic processing resource Sj expected to be activated at the first point of time.

Abstract: The present invention provides a system capable of properly controlling the switching of the operation state of each of a plurality of arithmetic processing resources according to an increase or a decrease in an arithmetic processing load. A distributed processing control system 10 includes a load estimation unit 11 that estimates an estimation arithmetic processing load at a first point of time in a future from a reference point of time, and a state control unit 12 that starts the processing for switching the operation state of an arithmetic processing resource Sj so as to satisfy a first condition, in which the estimated arithmetic processing load is included in a predetermined range of an estimation processing capacity of the arithmetic processing resource Sj expected to be activated at the first point of time.

Abstract: According to one embodiment, a unit includes battery modules each including an assembled battery including battery cells and a monitoring device, a BMU to communicate with the battery modules, a first drawer holding the battery module, a second drawer holding the BMU, and a housing containing the first drawer and the second drawer. The first and second drawers include first composite connectors secured to a side of the housing, which is almost orthogonal to a direction in which to insert the drawers into the housing. The housing has second composite connectors which mate with the first composite connectors, thereby to connect communication lines between the monitoring device and the BMU and the main-circuit lines between the assembled batteries of the battery modules.

Abstract: According to one embodiment, an interlocking device for a battery unit board includes a housing, a battery unit that is arranged in the housing, a switch that is electrically connected to the battery unit, and an interlocking mechanism that allows the movement of the battery unit when the switch is opened, and that inhibits the battery unit from being drawn from the housing when the switch is closed.

Abstract: An inspection device carries out beam scanning on a stable scanning cycle by enabling flexible change of various scanning sequences according to inspection conditions thereof, and at the same time, eliminates as much unevenness as possible in scanning cycle which hinders stabilization of charging. A beam scanning scheduler schedules beam scanning based on an inputted scanning condition, and a programmable sequencer carries out beam scanning control according to a beam scanning schedule generated by the beam scanning scheduler. The scanning scheduler calculates scanning line reference coordinates on a scanning-line-by-scanning-line basis, based on the scanning condition, and issues a scanning cycle trigger. The programmable sequencer controls supply timing of the scanning line reference coordinates and a scanning position on an in-line pixel-by-pixel basis, based on line scanning procedure information and the scanning cycle trigger provided from the beam scanning scheduler.

Abstract: An inspection device which carries out beam scanning on a stable scanning cycle by enabling flexible change of various scanning sequences according to inspection conditions thereof, and at the same time, eliminating as much unevenness as possible in scanning cycle which hinders stabilization of charging, is provided. Beam scanning scheduling means for scheduling beam scanning based on an inputted scanning condition, and a programmable sequencer which carries out beam scanning control according to a beam scanning schedule generated by the beam scanning scheduling means, are provided. The scanning scheduling means calculates scanning line reference coordinates on a scanning-line-by-scanning-line basis, based on the scanning condition, and issues a scanning cycle trigger.

Abstract: According to one embodiment, a unit includes battery modules each including an assembled battery including battery cells and a monitoring device, a BMU to communicate with the battery modules, a first drawer holding the battery module, a second drawer holding the BMU, and a housing containing the first drawer and the second drawer. The first and second drawers include first composite connectors secured to a side of the housing, which is almost orthogonal to a direction in which to insert the drawers into the housing. The housing has second composite connectors which mate with the first composite connectors, thereby to connect communication lines between the monitoring device and the BMU and the main-circuit lines between the assembled batteries of the battery modules.

Abstract: When an inspection apparatus of a semiconductor device repeatedly executes computation of prescribed area data, such as image processing for detecting defects, procedures for commanding, data load, computation, and data store need to be repeated the number of times of the computation. This may impose a limitation on the speeding up of the operation. In addition, when performing parallel computation by a high-capacity image processing system for handling minute images, a lot of processors are needed, resulting in an increase in cost.

Abstract: The present invention has a subject to provide an apparatus that optimizes scanning in accordance with circumstances or purposes, reduces distortion of images, and improves throughput, image quality, and defect detection rate by controlling deflection of a charged particle beam in a stage tracking system.

Abstract: A semiconductor inspecting apparatus includes: a buffer memory whose width is matched to the greater of parallel bus width and the width of the number of serial lanes; a preceding stage bus switching unit that fills the buffer memory with input data without making a free space; equivalent transmission capacity conversion including a following stage bus switching unit that fills read data to the width of an arbitrary number of serial lanes without making a free space; a preceding stage bus switching unit that fills a buffer memory with input data without making a free space; and equivalent transmission capacity inverse conversion including a following stage bus switching unit that fills a parallel bus of arbitrary width with data read from a buffer memory without making a free space.

Abstract: The present invention relates to a DRAM stacked packages, a DIMM, a method for testing them, and a semiconductor manufacturing method. According to the present invention, there is provided a DRAM stacked package comprising: a plurality of stacked DRAMs; external terminals to which test equipment is connected, said external terminals being used to input/output at least address, command, and data; and an interface chip provided between said plurality of stacked DRAMs and said external terminals. The plurality of DRAMs and the interface chip are implemented on a package. The interface chip comprises: a test circuit including: an algorithmic pattern generator for generating a test pattern used to test the plurality of DRAMs; applying circuits for applying said generated test pattern to the plurality of DRAMs; and a comparator for comparing each response signal received from the plurality of DRAMs with an expected value for judgment.

Abstract: The present invention has a subject to provide an apparatus that optimizes scanning in accordance with circumstances or purposes, reduces distortion of images, and improves throughput, image quality, and defect detection rate by controlling deflection of a charged particle beam in a stage tracking system.

Abstract: A semiconductor inspecting apparatus includes: a buffer memory whose width is matched to the greater of parallel bus width and the width of the number of serial lanes; a preceding stage bus switching unit that fills the buffer memory with input data without making a free space; equivalent transmission capacity conversion including a following stage bus switching unit that fills read data to the width of an arbitrary number of serial lanes without making a free space; a preceding stage bus switching unit that fills a buffer memory with input data without making a free space; and equivalent transmission capacity inverse conversion including a following stage bus switching unit that fills a parallel bus of arbitrary width with data read from a buffer memory without making a free space.

Abstract: A testing circuit using ALPG is mounted in a testing board in which sockets for mounting semiconductor memories as devices to be tested in the board is mounted and a volatile memory for storing a data table for generating a random pattern is provided in the testing circuit so that a test using a test pattern having no regularity is performed using the data table in addition to a test using a test pattern having regularity generated by the ALPG.

Abstract: When an inspection apparatus of a semiconductor device repeatedly executes computation of prescribed area data, such as image processing for detecting defects, procedures for commanding, data load, computation, and data store need to be repeated the number of times of the computation. This may impose a limitation on the speeding up of the operation. In addition, when performing parallel computation by a high-capacity image processing system for handling minute images, a lot of processors are needed, resulting in an increase in cost.

Abstract: Semiconductor testing equipment according to the present invention comprises: an algorithmic pattern generator for generating a test pattern for testing a memory under test and applying the pattern to the memory under test; a comparator for comparing a response signal from the memory under test and an expected value from tho algorithmic pattern generator; a fail address acquisition part for storing an address of the memory under test (fail address) when a result compared by the comparator is failed; a fail address analysis part for analyzing the failed address and calculating the address to be repaired (repair address); and a cycle-pattern generator for redundancy processing for inserting the address to be repaired into a test pattern and applying the address to the memory under test, so that even when capacity of the semiconductor memory is increased, a fabrication yield thereof is raised by testing the memory after the packaging and by performing the redundancy processing of a defective.

Abstract: A stacked type semiconductor device comprising: a baseboard having a terminal row formed at an end in which connecting terminals is arranged linearly and having a wiring pattern connected to the connecting terminals and external terminals; semiconductor chips having a pad row in which pads is arranged linearly in parallel to the terminal row and being stacked on the baseboard; and interposer boards having a wiring layer including a plurality of wires arranged in parallel with the same length for connecting between pads of the pad row and connecting terminals of the terminal row.

Abstract: The present invention relates to a DRAM stacked packages, a DIMM, a method for testing them, and a semiconductor manufacturing method. According to the present invention, there is provided a DRAM stacked package comprising: a plurality of stacked DRAMs; external terminals to which test equipment is connected, said external terminals being used to input/output at least address, command, and data; and an interface chip provided between said plurality of stacked DRAMs and said external terminals. The plurality of DRAMs and the interface chip are implemented on a package. The interface chip comprises: a test circuit including: an algorithmic pattern generator for generating a test pattern used to test the plurality of DRAMs; applying circuits for applying said generated test pattern to the plurality of DRAMs; and a comparator for comparing each response signal received from the plurality of DRAMs with an expected value for judgment.

Abstract: A signature circuit, i.e., a random-number generating circuit, is provided in a memory test apparatus. Also, a signature circuit is provided in each of devices-under-test. This configuration allows the large number of semiconductor integrated-circuit devices to be tested at one time with a high efficiency. This condition realizes a tremendous reduction in the test cost.

Abstract: The present invention aims at performing a semiconductor integrated circuit defect analysis with a simplified analysis apparatus and simplifying a defect analysis work. A defect analysis apparatus for a semiconductor integrated circuit is characterized in that a presence/absence of a defect is detected by irradiating an electromagnetic field from a probe to the semiconductor integrated circuit and detecting an electric characteristic variation such as a power supply current variation in the semiconductor integrated circuit.