Abstract: A silver halide color light-sensitive material is disclosed. The light-sensitive material comprises a support and a silver halide emulsion layer provided on the support. The emulsion layer comprises silver halide grains which have been formed in the presence of a complex of rhenium, molybdenum, iridium, rhodium, ruthenium, osmium, cadmium, zinc, palladium, platinum, gold, iron, nickel, cobalt, tungsten, or chromium each having at least one cyanate ligand, isocyanate ligand or fluminate ligand. The light-sensitive material is high in speed, low in fog and excellent in reciprocity low failure characteristics.

Abstract: A reflective silver halide photographic light-sensitive material is disclosed. The light-sensitive material comprises a reflective support having thereon a silver halide emulsion layer wherein the support have an oxygen permeability of not more than 2.0 ml/m.sup.2 .multidot.hr.multidot.atm and the silver halide emulsion layer contains a magenta coupler represented by the following Formula I; ##STR1## wherein Ar is an aryl group; Y is a hydrogen atom or a substituent capable of splitting off upon reaction with the oxidation product of a color developing agent; X is a halogen atom, an alkoxy group or an alkyl group; R is a strait- or branched-chain alkyl group having 1 to 20 carbon atoms; J is a strait- or branched-chain alkylene group; and n is an integer of from 0 to 4, when n is 2 or more, the plurality of Xs may be the same or different. The light-sensitive material is excellent in red color reproducibility and light fastness of red colored images.

Abstract: An amplifier circuit of a symmetrical type is implemented with load transistors 1, 3, 5, 6 and input transistors 2, 4. Load transistors 1, 5 and input transistor 2 constitute a first inverter, and load transistors 3, 6 and input transistor 4 constitute a second inverter. A change in the output potential of each inverter is transmitted to a load transistor of the other inverter and increases the fluctuation of the potential of an output signal. A transistor 9 or 10 for current control is arranged between an input transistor and ground or between a load transistor and a power supply. The transistor 9 or 10 for current control interrupts through current when operation of the amplifier circuit is unnecessary and enhances the gain when the amplifier circuit is on operation. The gain is enhanced by setting the conductance of the load transistor and the conductance of the input transistor on predetermined conditions.

Abstract: The present invention relates to a glass blank for producing optical element used for the press molding thereof, having a core glass and a surface layer covering at least the optically functional surface of the core glass. The surface layer consists of an evaporation glass. This invention also relates to the technique to mold a glass lens using the glass blank.

Abstract: In an active mode, a transistor 61 or 63 is turned on, so that a reference voltage generator circuit 1 and an internal voltage correcting circuit 2 are activated. Consequently, an internal voltage V.sub.INT which is stepped down is applied to an internal main circuit 7. Conversely, in a standby mode, a transistor 61 or 63 is turned off, so that the reference voltage generator circuit 1 and the internal voltage correcting circuit 2 are inactivated. Consequently, the current does not flow in the reference voltage generator circuit 1 and the internal voltage correcting circuit 2, resulting in reduction of a consumption power. Simultaneously, a transistor 62 or 64 is turned on, so that a source voltage Ext.Vcc is directly applied to the internal main circuit 7 through the transistor 62 or 23. Thereby, operation conditions of logic circuits in the internal main circuit 7 are maintained.

Abstract: A circuit for repairing a defective memory cell is provided between a row or column decoder and a memory cell array. When the decoder has n output lines, the memory cell array includes at least (N+1) row or column lines, where n is an integer. The repair circuit includes connection circuit for connecting the output lines of the decoder to the row or column lines, and a circuit for defining the connection of the connection circuit. The connection circuit includes n switching elements each of which is operable to connect one output line of the decoder to at least two row or column lines. The defining circuit defines the connection path of each switching element such that the output lines of the decoder is connected in one to one correspondence to successively located row or column lines excluding a row or column line connecting a defective memory cell. The defining circuit includes a series of laser programmable fuse elements provided between an operation voltage supply and a ground line.

Abstract: An input protective apparatus for a semiconductor device (Q3) comprises an MOS transistor (Q4) having a thick gate insulating film formed therein. The MOS transistor (Q4) has one active layer connected to an input terminal (11) through a second resistor element (R2) and connected to a semiconductor device (Q3) to be protected through a first resistor element (R1), and an other active layer connected to a ground terminal. The input protective apparatus is adapted such that a resistance value R.sub.1 of a first resistor element (R1) and a resistance value R.sub.2 of the second resistor element (R2) satisfy the relation R.sub.1 >R.sub.2, and the on-resistance R.sub.3 of the MOS transistor (Q4) and the resistance value R.sub.2 satisfy the relation R.sub.3 <<R.sub.2.

Abstract: In a static random access memory, when address signals change, one-shot pulses are responsively generated. A detection signal obtained by ORing the one-shot pulses is employed as an equalize signal. Potentials of a bit line pair is equalized in response to the equalize signal. A write inhibiting signal having a pulse width larger than that of the equalize signal is generated by a pulse width increasing circuit. A write operation of data is inhibited in response to the write inhibiting signal.

Abstract: A vibration wave motor for frictionally driving a movable member contacting, under pressure, a vibration member, by a vibration wave generated in the vibration member, includes at least a contact area of the movable member which is to contact to the vibration member and has an alumite film thereon irradiated with a high energy density beam.

Abstract: A semiconductor differential amplifier includes first and second MOS transistors of a first conductivity type acting as driver transistors, and third through sixth MOS transistors of a second conductivity type acting as load transistors. First and second input terminals are respectively connected to gate terminals of the first and fifth, and second and sixth transistors. Therefore, since input signals are applied to transistors of both the load and driver sections of the amplifier, the amplifier exhibits a higher sensitivity for detecting relatively small differences between the voltage at the first input terminal and the voltage at the second input terminal.

Abstract: A Viterbi decoder synchronization circuit comprises a phase shifter for introducing a variable amount of delay time to a received bit stream of convolutional codes in response to a control signal applied thereto with respect to a word synchronization signal which is derived from the bit stream. A first detector detects maximum and minimum metric values of the Viterbi decoder. A second detector detects the difference between the detected maximum and minimum metric values for coupling to an integrator. The output of the integrator is applied to a third detector which detects when the integrator output reaches a value indicative of a word-in-sync or word-out-of-sync condition. A phase shift signal is generated in response to an output signal from the third detector and applied to the phase shifter as the control signal.

Abstract: A Viterbi decoder synchronization circuit comprises a circuit that derives a word synchronization signal from a received bit stream of convolutional codes. A first detector detects a maximum of metric values derived from the Viterbi decoder at different locations in time. A memory is provided for storing therein the address codes derived at different times and the maximum metric values detected by the first detector. A second detector is connected to the memory for detecting the presence of a path between the states addressed by the address codes stored in the memory. An integrator is connected to the second detector to integrate its output signal. To the integrator is connected a third detector which detects when the integrator output reaches a value indicative of one of word-in-sync and word-out-of-sync conditions of the Viterbi decoder. A phase shift signal is generated in response to an output signal from the third detector and applied to a phase shifter to introduce a delay time to the bit stream.

Abstract: A frame synchronizing equipment is disclosed which enables the TDMA technique to be used in a mobile communication system or a small-scale stationary communication system and requires no reference station. Plural radio channels separated from one another on a time-sharing basis are monitored upon initiation of a call by one of plural radio stations to detect the presence of a unoccupied channel. When an occupied channel followed by an unoccupied channel is detected, a pulse is extracted in a frame period synchronized with a burst signal of the occupied channel immediately preceding the unoccupied channel. A phase synchronization oscillating circuit generates a frame synchronization signal in synchronism with the extracted pulse.