Abstract: When binary pixel data is written to a pixel circuit, of an H-level (3V) and a L-level (0V), a voltage of the level indicating the binary pixel data is held at a first node, and a voltage of the inverted level thereof is held at a second node. The first and second nodes are connected to a third node via N-channel transistors, respectively, and first and second selection control signals are supplied to gate terminals of the transistors, respectively. Voltage levels of the first and second selection control signals are periodically switched between 5V indicating the H-level and 0V indicating the L-level in a mutually inverted manner. As a result, the voltage of the first node and the voltage of the second node are alternately selected and applied to a pixel electrode of a display element.

Abstract: When binary pixel data is written to a pixel circuit, of an H-level (3V) and a L-level (0V), a voltage of the level indicating the binary pixel data is held at a first node, and a voltage of the inverted level thereof is held at a second node. The first and second nodes are connected to a third node via N-channel transistors, respectively, and first and second selection control signals are supplied to gate terminals of the transistors, respectively. Voltage levels of the first and second selection control signals are periodically switched between 5V indicating the H-level and 0V indicating the L-level in a mutually inverted manner. As a result, the voltage of the first node and the voltage of the second node are alternately selected and applied to a pixel electrode of a display element.

Abstract: A liquid crystal display device includes a first substrate, a second substrate, a liquid crystal layer, and a plurality of pixels. Each of the pixels has a reflection region for performing display in a reflective mode. The first substrate includes a pixel electrode provided in each of the pixels and a reflection layer positioned opposite to the liquid crystal layer with respect to the pixel electrode. The reflection layer has a first region positioned in each of the pixels and a second region positioned between any two pixels adjacent to each other. Voltages of an identical polarity are applied to the liquid crystal layer for any two pixels adjacent to each other in a row direction, for any two pixels adjacent to each other in a column direction, or for all the pixels.

Abstract: A liquid crystal display device includes a first substrate, a second substrate, a vertical alignment liquid crystal layer, and a plurality of pixels. Each of the pixels includes a reflective region for performing display in a reflection mode. The first substrate includes a reflective electrode including a first region located within each of the plurality of pixels and a second region located between any two pixels, of the plurality of pixels, adjacent to each other, a transparent insulating layer provided to cover the reflective electrode, and a pixel electrode formed from a transparent conductive material and provided on the transparent insulating layer in each of the plurality of pixels. The second substrate includes a counter electrode provided to be opposite to the pixel electrode and the reflective electrode.

Abstract: A liquid crystal display device includes a first substrate, a second substrate, a vertical alignment liquid crystal layer, and a plurality of pixels. Each of the pixels includes a reflective region for performing display in a reflection mode. The first substrate includes a reflective electrode including a first region located within each of the plurality of pixels and a second region located between any two pixels, of the plurality of pixels, adjacent to each other, a transparent insulating layer provided to cover the reflective electrode, and a pixel electrode formed from a transparent conductive material and provided on the transparent insulating layer in each of the plurality of pixels. The second substrate includes a counter electrode.

Abstract: A display device includes a pixel unit, a binary driver, and a timing generator. The display device is an active matrix display device configured to receive a data signal including image data and other data different from the image data. The pixel unit includes a memory configured to store the image data. The binary driver includes a first holding circuit configured to hold the image data and at least one second holding circuit configured to hold the other data. The timing generator is configured to generate a drive signal used for driving the binary driver.

Abstract: A liquid crystal display device includes a first substrate, a second substrate, a vertical alignment liquid crystal layer, and a plurality of pixels. Each of the pixels includes a reflective region for performing display in a reflection mode. The first substrate includes a reflective electrode including a first region located within each of the plurality of pixels and a second region located between any two pixels, of the plurality of pixels, adjacent to each other, a transparent insulating layer provided to cover the reflective electrode, and a pixel electrode formed from a transparent conductive material and provided on the transparent insulating layer in each of the plurality of pixels. The second substrate includes a counter electrode provided to be opposite to the pixel electrode and the reflective electrode.

Abstract: A liquid crystal display device includes a first substrate, a second substrate, a vertical alignment liquid crystal layer, and a plurality of pixels. Each of the pixels includes a reflective region for performing display in a reflection mode. The first substrate includes a reflective electrode including a first region located within each of the plurality of pixels and a second region located between any two pixels, of the plurality of pixels, adjacent to each other, a transparent insulating layer provided to cover the reflective electrode, and a pixel electrode formed from a transparent conductive material and provided on the transparent insulating layer in each of the plurality of pixels. The second substrate includes a counter electrode.

Abstract: A plurality of pieces of serial data are supplied to a liquid crystal display device from an outside. An SI signal selection circuit switches processing target data to be captured between one piece of serial data included in the plurality of pieces of serial data and the plurality of pieces of serial data in accordance with a serial data selection signal. The processing target data captured by the SI signal selection circuit is converted into parallel data by a data conversion circuit. In accordance with one clock pulse of a serial clock, serial-parallel conversion processing is performed in parallel on a plurality pieces of serial data.

Abstract: A display device includes a pixel unit, a binary driver, and a timing generator. The display device is an active matrix display device configured to receive a data signal including image data and other data different from the image data. The pixel unit includes a memory configured to store the image data. The binary driver includes a first holding circuit configured to hold the image data and at least one second holding circuit configured to hold the other data. The timing generator is configured to generate a drive signal used for driving the binary driver.

Abstract: A data signal line drive circuit includes: a shift register including a plurality of unit circuits; a first latch portion including a plurality of first latch circuits; and a second latch portion including a plurality of second latch circuits. Here, the k-th (k is a natural number) second latch circuit is provided with first latch signals provided to (k+1)-th and subsequent first latch circuits as a second latch signal, so that the capturing of data signals at the second latch portion is split into two or more timings.

Abstract: A liquid crystal display device includes a first substrate, a second substrate, a liquid crystal layer, and a plurality of pixels. Each of the pixels has a reflection region for performing display in a reflective mode. The first substrate includes a pixel electrode provided in each of the pixels and a reflection layer positioned opposite to the liquid crystal layer with respect to the pixel electrode. The reflection layer has a first region positioned in each of the pixels and a second region positioned between any two pixels adjacent to each other. Voltages of an identical polarity are applied to the liquid crystal layer for any two pixels adjacent to each other in a row direction, for any two pixels adjacent to each other in a column direction, or for all the pixels.

Abstract: A data signal line drive circuit includes: a shift register including a plurality of unit circuits; a first latch portion including a plurality of first latch circuits; and a second latch portion including a plurality of second latch circuits. Here, the k-th (k is a natural number) second latch circuit is provided with first latch signals provided to (k+1)-th and subsequent first latch circuits as a second latch signal, so that the capturing of data signals at the second latch portion is split into two or more timings.

Abstract: A display device includes a reflective electrode, a driving circuit section, a wiring, and a wiring expansion section. The reflective electrode is divided into split electrodes arranged with spaces, which transmit light, respectively provided thereamong and reflects light. The driving circuit section drives the reflective electrode. The wiring is connected to at least the split electrodes and the driving circuit section and composed of a conductive material having a light transmission property. The wiring expansion section is formed to expand in the wiring to overlap the space.

Abstract: A plurality of pieces of serial data are supplied to a liquid crystal display device from an outside. An SI signal selection circuit switches processing target data to be captured between one piece of serial data included in the plurality of pieces of serial data and the plurality of pieces of serial data in accordance with a serial data selection signal. The processing target data captured by the SI signal selection circuit is converted into parallel data by a data conversion circuit. In accordance with one clock pulse of a serial clock, serial-parallel conversion processing is performed in parallel on a plurality pieces of serial data.

Abstract: A display device includes a reflective electrode, a driving circuit section, a wiring, and a wiring expansion section. The reflective electrode is divided into split electrodes arranged with spaces, which transmit light, respectively provided thereamong and reflects light. The driving circuit section drives the reflective electrode. The wiring is connected to at least the split electrodes and the driving circuit section and composed of a conductive material having a light transmission property. The wiring expansion section is formed to expand in the wiring to overlap the space.

Abstract: A shift register is realized having a simple construction with which it is possible to switch the scanning order of gate bus lines and the occurrence of an erroneous operation caused by a threshold voltage drop can be prevented. Unit circuits that make up the shift register are configured of: a thin film transistor in which a third clock is supplied to the gate terminal, the drain terminal is connected to a first node, and a first input signal (output signal of prior stage) is supplied to the source terminal; a thin film transistor in which a second clock is supplied to the gate terminal, the drain terminal is connected to the first node, and a second input signal (output signal of subsequent stage) is supplied to the source terminal; and a thin film transistor in which the gate terminal is connected to the first node, a first clock is supplied to the drain terminal, and the source terminal is connected to an output terminal.

Abstract: A shift register is configured by connecting unit circuits 1 in multiple stages. An output transistor Tr1 switches between whether or not to output a clock signal CKA in accordance with a gate potential. A set transistor Tr2 switches between whether or not to provide an output of an on-potential output unit 2 to a gate terminal of Tr1 in accordance with an output of a set control unit 3. The set control unit 3 controls a gate terminal of Tr2 into a floating state in part of a period during which a high-level potential is provided to the gate terminal of Tr1. The gate potential of Tr2 is raised by being pushed up, whereby a high-level potential without a threshold drop is provided to the gate terminal of Tr1, and rounding of an output signal OUT is decreased when the output signal OUT shifts to a high level. Accordingly, an operation margin with respect to fluctuation of a threshold voltage of the transistor is increased.

Abstract: A shift register is configured by connecting unit circuits 1 in multiple stages. An output transistor Tr1 switches between whether or not to output a clock signal CKA in accordance with a gate potential. A drain terminal of an initialization transistor Tra is connected to a gate terminal of the Tr1, and a source terminal thereof is connected to an output terminal OUT or a clock terminal CKA. The source terminal of the Tra is connected to a node which has a low-level potential at the time of initialization and has a potential at the same level as the clock signal when the clock signal having a high-level potential is outputted. Thus, at the time of outputting the clock signal having the high-level potential, application of a high voltage between the source and the drain of the Tra is prevented, and degradation and breakdown of the initialization transistor are prevented.

Abstract: A shift register is configured by connecting unit circuits 1 in multiple stages. An output transistor Tr1 switches between whether or not to output a clock signal CKA in accordance with a gate potential. A set transistor Tr2 switches between whether or not to provide an output of an on-potential output unit 2 to a gate terminal of Tr1 in accordance with an output of a set control unit 3. The set control unit 3 controls a gate terminal of Tr2 into a floating state in part of a period during which a high-level potential is provided to the gate terminal of Tr1. The gate potential of Tr2 is raised by being pushed up, whereby a high-level potential without a threshold drop is provided to the gate terminal of Tr1, and rounding of an output signal OUT is decreased when the output signal OUT shifts to a high level. Accordingly, an operation margin with respect to fluctuation of a threshold voltage of the transistor is increased.