Abstract: A washing machine according to the present invention is a new washing machine which is compact and can realize uniform and good washing. The plane shape of a washing tub 211 is an approximately rectangular inner shape which is defined by a bottom 213, a pair of long side walls 214a and 214b, and a pair of short side walls 215a and 215b. A pulsator 212 is so provided on the one long side wall 214b out of the pair of long side walls that its center axis 219 is perpendicular to the long side wall 214b. The diameter A of a disk 220 of the pulsator 212 is so set that W<A. Further, a projection 221 of the pulsator 212 is a projection which is long in the radial direction of the disk 220, so that the height thereof from the surface of the disk 220 is large on the side of the circumference of the disk 220. In the washing machine, the pulsator 212 is increased in the efficiency of agitation of wash water and laundry in the washing tub 211 while being longitudinally arranged.

Abstract: A MUSE sound decoder detects a broadcasting/non-broadcasting identification flag included in the control signals in an applied MUSE signal to determine whether the MUSE signal is broadcasted or non-broadcasted. The MUSE sound decoder further includes a frame synchronization protection circuit for protecting frame synchronization over a predetermined frame synchronization protection time period when the frame synchronization pattern is not detected at the proper timing. The frame synchronization protection circuit sets the frame synchronization protection time period to a long time period when the MUSE signal is determined to be a broadcasted MUSE signal, and to a short time period when the MUSE signal is determined to be a non-broadcasted MUSE signal. Appropriate muting of a sound signal can be carried out according to the condition of the received MUSE signal.

Abstract: A jitter correction circuit is a circuit for suppressing a jitter contained in a reproduced digital signal. This jitter correction circuit comprises a phase-locked loop circuit comprising a phase comparing circuit (9), a second low-pass filter (10), a second voltage control oscillator (11) and a second frequency dividing circuit (12). The phase-locked loop circuit provides an oscillation output which causes little influence to a jitter component contained in a reproduced signal digitally converted by an analog-to-digital converting circuit (1). The digitally converted reproduced signal is resampled in a sampling pulse generating circuit (13) and a resampling circuit (7) which operates based on the above stated phase-locked loop circuit. As a result, the resampling circuit (7) provides an output having a considerably decreased amount of jitter.