Abstract: Aspects of the disclosed technology relate to techniques for using hotspot simulation to make wafer rework decisions. Metrology data of photoresist patterns created based on a layout design for a circuit design by a photolithographic processing step are received during a lithographic process. Hotspots of interest are selected based on comparing the metrology data with simulated metrology data associated with hotspots. The simulated metrology data and information of the hotspots are generated by performing lithographic simulation on the layout design before the lithographic process and stored in a library of potential hotspots. Lithography simulation is performed on the selected hotspots of interest using process conditions of the photolithographic processing step to generate simulated hotspot data. The simulated hotspot data are analyzed to determine whether rework of the one or more wafers or a wafer lot to which the one or more wafers belong is needed.

Abstract: Aspects of the disclosed technology relate to techniques for using hotspot simulation to make wafer rework decisions. Metrology data of photoresist patterns created based on a layout design for a circuit design by a photolithographic processing step are received during a lithographic process. Hotspots of interest are selected based on comparing the metrology data with simulated metrology data associated with hotspots. The simulated metrology data and information of the hotspots are generated by performing lithographic simulation on the layout design before the lithographic process and stored in a library of potential hotspots. Lithography simulation is performed on the selected hotspots of interest using process conditions of the photolithographic processing step to generate simulated hotspot data. The simulated hotspot data are analyzed to determine whether rework of the one or more wafers or a wafer lot to which the one or more wafers belong is needed.

Abstract: A system for producing mask layout data retrieves target layout data defining a pattern of features, or portion thereof and an optimized mask layout pattern that includes a number of printing and non-printing features. Mask layout data for one or more subresolution assist features (SRAFs) is then defined to approximate one or more non-printing features of the optimized mask layout pattern.

Abstract: A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.

Abstract: A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.

Abstract: A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.

Abstract: The system and method performs optical proximity correction on an integrated circuit (IC) mask design by initially performing optical proximity correction on a library of cells that are used to create the IC. The pre-tested cells are imported onto a mask design. All cells are placed a minimum distance apart to ensure that no proximity effects will occur between elements fully integrated in different cells. A one-dimensional optical proximity correction technique is performed on the mask design by performing proximity correction only on those components, e.g., lines, that are not fully integrated within one cell.

Abstract: A method of providing etched alignment marks on a semiconductor workpiece that has a substantially planar surface, such as one that has been polished, for supporting accurate alignment of the workpiece in subsequent process operations. The surface of the semiconductor workpiece includes two layers of materials that abut at the workpiece surface. For example, the workpiece may include a layer of insulative material such as silicon dioxide forming several vias and a layer of conductive material such as tungsten forming plugs in the vias. The method includes etching the substantially planar surface to reduce a height of one of the materials below the height of the other material. For example, the tungstein plugs can be etched to a height that is below the height of the surrounding silicon dioxide. The location where the silicon dioxide abuts the tungsten produces a small bump. This bump then serves as an alignment mark for subsequent operations.