Abstract: A new method is provided for the creation of a solder bump. Conventional methods are initially followed, creating a patterned layer of Under Bump Metal over the surface of a contact pad. A layer of photoresist is next deposited, this layer of photoresist is patterned and developed creating a resist mask having a T-shape opening aligned with the contact pad. This T-shaped opening is filled with a solder compound, creating a T-shaped layer of solder compound on the surface of the layer of UBM. The layer of photoresist is removed, exposing the Created T-shaped layer of solder compound, further exposing the layer of UBM. The layer of UBM is etched using the T-shaped layer of solder compound as a mask. Reflow of the solder compound results in creating a solder ball.

Abstract: A new method is provided for the creation of a solder mask for solder bump formation. A passivation layer is deposited on the semiconductor surface in the surface of which a contact pad has been provided, an opening is created in the layer of passivation that partially exposed the surface of the contact pad. A layer of UBM metal is deposited and patterned, limiting the layer of UBM to overlying and contacting the contact pad of the solder bump. A layer of elastomer is blanket deposited over the surface and patterned, creating an opening overlying the opening created in the layer of passivation, exposing the layer of UBM. The exposed surface of the layer of UBM is electroplated with a layer of solder, using the opening created in the layer of elastomer as the self-aligned electroplating opening. A step of reflow of the electroplated solder and the layer of elastomer completes the process of the invention, creating a solder bump surrounded by a layer of cured elastomer.

Abstract: A process for forming self-aligned, twin well regions for a CMOS device, without the use of an oxidation retarding silicon nitride layer, has been developed. A first ion implantation procedure is used to place N type ions in a first portion of a semiconductor substrate, followed by a wet thermal oxidation procedure resulting in the growth of a thick silicon dioxide layer on the N type ions, in the first portion of the semiconductor substrate, while growing a thin silicon dioxide layer on a second portion of the lightly doped, P type semiconductor substrate. A second ion implantation procedure places P type ions through the thin silicon dioxide layer, into the second portion of the semiconductor substrate, while the thick silicon dioxide layer prevents the P type ions from reaching the first portion of the semiconductor substrate.

Abstract: Within a method for fabricating an microelectronic fabrication there is first provided a substrate employed within an optoelectronic microelectronic fabrication, where the substrate comprises an optoelectronic microelectronic device which is in electrical communication with a bond pad formed over the substrate. There is then processed, when fabricating the substrate to form the optoelectronic microelectronic fabrication, the substrate in the absence of optoelectronically transducable radiation, in order to attenuate corrosion of the bond pad. The method is particularly useful for forming a color filter sensor image array optoelectronic microelectronic fabrication comprising multiple photoresist based patterned colored filter layers.

Abstract: A method of forming a high polysilicon resistor over a dielectric layer, comprising the following steps. A polysilicon resistor over a semiconductor structure is provided. The polysilicon resistor has a doped polysilicon layer having a first voltage coefficient of resistance and grain boundaries having a first trapping density. A to a first level of DC current is provided for a predetermined duration through the doped polysilicon layer to stress the doped polysilicon layer to partially melt the doped polysilicon layer without causing breakdown of the doped polysilicon layer. The to a first level of DC current is removed to allow recrystallization of the melted doped polysilicon layer, whereby the recrystallized doped polysilicon layer has a second voltage coefficient of resistance less than the first voltage coefficient of resistance and grain boundaries having a second trapping density that is less than the first trapping density. This makes the Rs of the polysilicon to be stable and saturated.

Abstract: A new method of forming a polysilicon resistor having reduced resistance variations by using an LPCVD silicon nitride cap over the polysilicon resistor is described. A field oxide layer is provided overlying a semiconductor substrate. A polysilicon layer is deposited overlying the field oxide layer and etched away where it is not covered by a mask to form a polysilicon resistor. The polysilicon resistor is oxidized to form an oxide layer on all surfaces of the polysilicon resistor. A silicon nitride barrier layer is deposited overlying the oxide layer. An interlevel dielectric layer is dpeosited overlying the silicon nitride barrier layer. Contact openings are etched through the interlevel dielectric layer, silicon nitride barrier layer, and oxide layer to the polysilicon resistor. The contact openings are filled with a metal layer which is patterned.

Abstract: A new method of local oxidation using nitrogen implant to reduce the growth of a bird's beak is described. An oxide layer is provided over the surface of a semiconductor substrate. A first silicon nitride layer is deposited overlying the oxide layer. An opening is etched through the first silicon nitride layer to the oxide layer where the device isolation region is to be formed. Nitrogen ions are implanted through the oxide layer to form a nitrogen implanted area within the semiconductor substrate within the opening. A second silicon nitride layer is deposited overlying the first silicon nitride layer and the oxide layer within the opening. The second silicon nitride layer is etched away to leave spacers on the sidewalls of the first silicon nitride layer. The oxide layer and the nitrogen implanted area of the semiconductor substrate within the opening are etched away where they are not covered by the spacers.

Abstract: A field oxide region and method of forming a field oxide region using a LOCOS process and nitride spacers formed on the sidewalls of the field oxide regions. During the LOCOS process recesses are formed in the field oxide which result in poor step coverage during successive process steps. Nitride spacers are formed on the sidewalls of the field oxide covering the recesses. The spacers provide a smooth surface over the field oxide and improved step coverage during subsequent process steps.

Abstract: The contact or via hole etch pattern photomask used in fabrication of integrated circuits is modified to provide a series of grooves or trenches to be etched in the silicon oxide layer simultaneously with the contact or via holes. These trenches, after deposition and planarization of tungsten metal layer, afford regenerated alignment marks with sharply-defined edges even after deposition of a second conductive layer.

Abstract: A process has been developed in which an aluminum based, interconnect structure overlies a tungsten plug structure, in a small diameter contact hole. The tungsten plug is formed via RIE removal of unwanted tungsten, from areas other then the contact hole using a halogen containing etchant, and using a RIE overetch cycle that creates an unwanted crevice in the center of the tungsten plug. A post RIE anneal, in a nitrogen ambient removes moisture from surrounding dielectric layers and also forms a protective, nitrogen containing tungsten layer, filling the crevice in the tungsten plug. The filling of the crevice allows a planar overlying aluminum based, interconnect structure to be obtained.

Abstract: A method of forming high contrast alignment marks on an integrated circuit wafer for patterning a layer of highly reflective electrode metal is described. A method of patterning a layer of highly reflective metal on an integrated circuit wafer using high contrast alignment marks is also described. Due to a difference in height of alignment marks and contact metal surrounding the alignment marks the alignment marks are transferred to the contour of the highly reflective electrode metal. A non reflective layer of bottom anti-reflection coating material is then used to provide high contrast at the location where the edges of the alignment marks are transferred to the highly reflective electrode metal.

Abstract: A method for making a polycide-to-polysilicon capacitor having an improved breakdown voltage is described. A first layer of doped polysilicon is formed over a silicon substrate. A silicide layer is formed over the first layer of doped polysilicon. An oxide layer is formed over the silicide layer, and the silicide layer is then annealed. A second layer of doped polysilicon is formed over the oxide layer. The second layer of doped polysilicon is patterned to form a top plate of the capacitor. The oxide layer is removed except under the top plate of the capacitor, where it acts as a capacitor dielectric. The first layer of doped polysilicon and the silicide layer are patterned to form a polycide bottom plate of the capacitor.

Abstract: A method for forming a CMOS device, with improved yield, performance and reliability characteristics, has been developed. Yield improvements have been addressed by the use of a dual insulator spacer, used to reduce the risk of salicide bridging, as well as the use of pocket implantation regions, used to reduce punchthrough leakage. An ultra shallow junction extension region has been created in a peripheral channel region, reducing the resistance of this region, thus enhancing the performance of the CMOS device. In addition, ultra lightly doped source and drain regions are used to relax reliability concerns, regarding hot electron injection.

Abstract: A new method of local oxidation using an oxynitrided pad oxide layer to suppress the growth of a bird's beak is described. An oxide layer is provided over the surface of a semiconductor substrate. The oxide layer is annealed in a nitrogen atmosphere whereby the oxide layer is nitrided. The nitrided oxide layer is then reoxidized. A silicon nitride layer is deposited overlying the oxide layer. Portions of the silicon nitride and oxide layers not covered by a mask pattern are etched through to provide an opening exposing the portion of the semiconductor substrate that will form the field oxidation. The silicon substrate within the opening is oxidized wherein the semiconductor substrate is transformed to silicon dioxide wherein the nitrided oxide layer suppresses the formation of the bird's beak whereby the field oxidation is formed with a small bird's beak. The remaining oxide and silicon nitride layers are removed completing the field oxidation of the integrated circuit.

Abstract: The preservation of alignment marks and identification marks throughout the multitude of processing steps employed for the manufacture of integrated circuit chips often requires the inclusion of additional operations which impact production cost and product throughput. Current increased utilization of global planarization operations such as chemical-mechanical-polishing have forced the inclusion of additional window opening lithographic steps requiring additional masks and etch operations to keep these marks from being obscured. This invention provides a technique and a reticle design for clearing and preserving alignment and wafer identification marks through planarization and metallization levels with improved throughput and without the need for additional reticles to clear the marks. The alignment mark areas are exposed by a large clear-out window located in the frame area of the contact/via reticle while the wafer identification marks are accommodated in the same fashion by the metal pattern reticle.

Abstract: A method for improving the source/drain resistance in the fabrication of an integrated circuit device is described. Gate electrodes are formed on the surface of a semiconductor substrate. Lightly doped regions are implanted into the semiconductor substrate using the gate electrodes as a mask. First spacers are formed on the sidewalls of the gate electrodes. Second spacers are formed on the sidewalls of the first spacers. Heavily doped source and drain regions are implanted into the semiconductor substrate using the gate electrodes and first and second spacers as a mask. Thereafter, the second spacers are removed. A titanium layer is deposited by chemical vapor deposition over the substrate whereby titanium silicide is formed overlying the gate electrodes and overlying the source and drain regions and whereby elemental titanium is deposited overlying the first spacers wherein the titanium silicide overlying the source and drain regions improves the source/drain resistance. The elemental titanium is removed.

Abstract: This invention describes a new method for forming self-aligned silicide for application in MOSFET, and a new structure of MOSFET device featuring elevated source and drain, with the objectives of reducing silicide penetration into the source and drain junctions, of eliminating junction spikes, of obtaining smoother interface between the silicide and the silicon substrate, and of reducing the chance of bridging of the silicides on the gate and on the source and drain. The new structure is made by depositing an amorphous layer of silicon on a silicon substrate already patterned with field oxide, gate oxide, polysilicon gate, and silicon nitride spacer on the gate sidewalls. Novel oxide sidewall spacers are then created by first implanting nitrogen into the horizontal surface of the amorphous silicon layer and subsequently thermally oxidizing the part of the amorphous silicon on the vertical sidewalls that is not exposed to nitrogen implantation. A dopant implantation followed by an annealing at 600.degree. C.

Abstract: A method for forming a CMOS device, with improved yield, performance and reliability characteristics, has been developed. Yield improvements have been addressed by the use of a dual insulator spacer, used to reduce the risk of salicide bridging, as well as the use of pocket implantation regions, used to reduce punchthrough leakage. An ultra shallow junction extension region has been created in a peripheral channel region, reducing the resistance of this region, thus enhancing the performance of the CMOS device. In addition, ultra lightly doped source and drain regions are used to relax reliability concerns, regarding hot electron injection.

Abstract: A process has been developed in which an aluminum based, interconnect structure overlies a tungsten plug structure, in a small diameter contact hole. The tungsten plug is formed via RIE removal of unwanted tungsten, from areas other then the contact hole using a halogen containing etchant, and using a RIE overetch cycle that created an unwanted crevice in the center of the tungsten plug. A post RIE anneal, in a nitrogen ambient removes moisture from surrounding dielectric layers and also forms a protective, nitrogen containing tungsten layer, filling the crevice in the tungsten plug. The filling of the crevice allows a planar overlying aluminum based, interconnect structure to be obtained.

Abstract: An improved and new process for chemical/mechanical planarization (CMP) of a substrate surface, wherein the endpoint for the planarization process is detected by monitoring the temperature of the polishing pad with an infrared temperature measuring device, has been developed. The method allows endpoint to be detected in-situ at the polishing apparatus, without necessity to unload the substrate for visual inspection or performance of specialized, time-consuming, and costly thickness and/or surface topography measurements.