Abstract: Information specifying invalidating areas of a main memory is stored in an area specifying register. Each time a signal indicating an index address is input to a tag memory and a data memory, cached data of the index address of a data memory is output, a tag address is output from a tag memory. A combined address of the tag address and the index address indicates an address of the main memory from which data is written at the index address of the data memory. Thereafter, it is judged whether or not an area of each combined address of the main memory agrees with one of the invalidating areas. In case of the agreement of the area of each combined address and one invalidating area, the invalidating processing is performed for the cached data of the index address corresponding to the combined address.

Abstract: Information specifying invalidating areas of a main memory is stored in an area specifying register. Each time a signal indicating an index address is input to a tag memory and a data memory, cached data of the index address of a data memory is output, a tag address is output from a tag memory. A combined address of the tag address and the index address indicates an address of the main memory from which data is written at the index address of the data memory. Thereafter, it is judged whether or not an area of each combined address of the main memory agrees with one of the invalidating areas. In case of the agreement of the area of each combined address and one invalidating area, the invalidating processing is performed for the cached data of the index address corresponding to the combined address.

Abstract: A clock synchronizing circuit includes many sequential circuits which operate on the basis of the same clock signal. The sequential circuits sample input data and change output data at both rising and falling edges of the clock signal. The sequential circuits include an input selector circuit which selects either of two inputs in accordance with a test mode signal. The output of one sequential circuit is input into an input selector circuit of a subsequent sequential circuit. Thus, a scan pass is formed.

Abstract: In the asynchronous serial data transmission and/or reception conducted by an asynchronous serial data communication device, an asynchronous serial data receiving device as an asynchronous serial data receiver section inputs a count correction signal (15) from a count correction circuit (2), and a control signal generating circuit (1) that generates a data shift signal (120) controls the timing for outputting the data shift signal (120) in accordance with the count value correction signal (15). The time intervals during which a serial-to-parallel conversion circuit (3) samples a communication data (4) is changed as to each data bit in accordance with this data shift signal, so that the sampling interval can be set more precisely than just a multiple of integer of the operation clock (110), thereby to improve the baud.

Abstract: The clock synchronizing circuit is provided with many sequential circuits which operate on the basis of same clock signal. The sequential circuits carries out sampling of input data and changing of output data at both rising and falling edge of the clock signal. The sequential circuits include input selector circuit which select either of two inputs in accordance with a test mode signal. Output of one sequential circuit is input into an input selector circuit of subsequent sequential circuit. Thus, a series of scan pass SP is formed.