Patents by Inventor Shun Wu Lin
Shun Wu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8415254Abstract: A method is provided for fabricating a semiconductor device. The method includes removing a silicon material from a gate structure located on a substrate through a cycle including: etching the silicon material to remove a portion thereof, where the substrate is spun at a spin rate, applying a cleaning agent to the substrate, and drying the substrate; and repeating the cycle, where a subsequent cycle includes a subsequent spin rate for spinning the substrate during the etching and where the subsequent spin rate does not exceed the spin rate of the previous cycle.Type: GrantFiled: November 20, 2008Date of Patent: April 9, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Matt Yeh, Fan-Yi Hsu, Shun Wu Lin, Shu-Yuan Ku, Hui Ouyang
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Patent number: 8357617Abstract: Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process.Type: GrantFiled: February 16, 2009Date of Patent: January 22, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Matt Yeh, Shun Wu Lin, Chi-Chun Chen, Ryan Chia-Jen Chen, Yi-Hsing Chen, Chien-Hao Chen, Donald Y. Chao, Kuo-Bin Huang
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Patent number: 8268085Abstract: A method for cleaning a diffusion barrier over a gate dielectric of a metal-gate transistor over a substrate is provided. The method includes cleaning the diffusion barrier with a first solution including at least one surfactant. The amount of the surfactant of the first solution is about a critical micelle concentration (CMC) or more. The diffusion barrier is cleaned with a second solution. The second solution has a physical force to remove particles over the diffusion barrier. The second solution is substantially free from interacting with the diffusion barrier.Type: GrantFiled: March 8, 2010Date of Patent: September 18, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Matt Yeh, Shun Wu Lin, Hui Ouyang
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Patent number: 8173504Abstract: A method for fabricating an integrated device is disclosed. A polysilicon gate electrode layer is provided on a substrate. In an embodiment, a treatment is provided on the polysilicon gate electrode layer to introduce species in the gate electrode layer and form an electrically neutralized portion therein. Then, a hard mask layer with limited thickness is applied on the treated polysilicon gate electrode layer. A tilt angle ion implantation is thus performing on the substrate after patterning the hard mask layer and the treated polysilicon gate electrode to from a gate structure.Type: GrantFiled: April 12, 2010Date of Patent: May 8, 2012Inventors: Matt Yeh, Fan-Yi Hsu, Shun Wu Lin, Hui Ouyang, Chi-Ming Yang
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Patent number: 8114721Abstract: A method of forming a FinFET device is provided. In one embodiment, a fin is formed on a substrate. A gate structure is formed over the fin, the gate structure having a dielectric layer and a conformal first polysilicon layer formed above the dielectric layer. An etch stop layer is formed above the first polysilicon layer and thereafter a second polysilicon layer is formed above the etch stop layer. The second polysilicon layer and the etch stop layer are removed. A metal layer is formed above the first polysilicon layer. The first polysilicon layer is reacted with the metal layer to silicide the first polysilicon layer. Any un-reacted metal layer is thereafter removed and source and drain regions are formed on opposite sides of the fin.Type: GrantFiled: December 15, 2009Date of Patent: February 14, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shun Wu Lin, Peng-Soon Lim, Matt Yeh, Ouyang Hui
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Patent number: 8048810Abstract: A method for fabricating a integrated circuit is disclosed. An exemplary method includes providing a substrate; forming a hard mask layer over the substrate; forming a patterned photoresist layer over the hard mask layer, such that portions of the hard mask layer are exposed; performing a dry etching process to remove the exposed portions of the hard mask layer; removing the patterned photoresist layer using at least one of a nitrogen plasma ashing and a hydrogen plasma ashing; and performing a wet etching process to remove remaining portions of the hard mask layer.Type: GrantFiled: January 29, 2010Date of Patent: November 1, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fang Wen Tsai, Jim Cy Huang, Shun Wu Lin, Li-Shiun Chen, Kuang-Yuan Hsu
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Publication number: 20110250725Abstract: A method for fabricating an integrated device is disclosed. A polysilicon gate electrode layer is provided on a substrate. In an embodiment, a treatment is provided on the polysilicon gate electrode layer to introduce species in the gate electrode layer and form an electrically neutralized portion therein. Then, a hard mask layer with limited thickness is applied on the treated polysilicon gate electrode layer. A tilt angle ion implantation is thus performing on the substrate after patterning the hard mask layer and the treated polysilicon gate electrode to from a gate structure.Type: ApplicationFiled: April 12, 2010Publication date: October 13, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Matt YEH, Fan-Yi HSU, Shun Wu LIN, Hui OUYANG, Chi-Ming YANG
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Publication number: 20110189847Abstract: A method for fabricating a integrated circuit is disclosed. An exemplary method includes providing a substrate; forming a hard mask layer over the substrate; forming a patterned photoresist layer over the hard mask layer, such that portions of the hard mask layer are exposed; performing a dry etching process to remove the exposed portions of the hard mask layer; removing the patterned photoresist layer using at least one of a nitrogen plasma ashing and a hydrogen plasma ashing; and performing a wet etching process to remove remaining portions of the hard mask layer.Type: ApplicationFiled: January 29, 2010Publication date: August 4, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fang Wen Tsai, Jim C.Y. Huang, Shun Wu Lin, Li-Shiun Chen, Kuang-Yuan Hsu
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Publication number: 20110143510Abstract: A method of forming a FinFET device is provided. In one embodiment, a fin is formed on a substrate. A gate structure is formed over the fin, the gate structure having a dielectric layer and a conformal first polysilicon layer formed above the dielectric layer. An etch stop layer is formed above the first polysilicon layer and thereafter a second polysilicon layer is formed above the etch stop layer. The second polysilicon layer and the etch stop layer are removed. A metal layer is formed above the first polysilicon layer. The first polysilicon layer is reacted with the metal layer to silicide the first polysilicon layer. Any un-reacted metal layer is thereafter removed and source and drain regions are formed on opposite sides of the fin.Type: ApplicationFiled: December 15, 2009Publication date: June 16, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shun Wu LIN, Peng-Soon Lim, Matt Yeh, Ouyang Hui
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Publication number: 20110097867Abstract: A method of fabricating a semiconductor device is provided. In one embodiment, a gate structure is formed on a substrate, the gate structure having a gate dielectric layer and a first polysilicon layer formed above the gate dielectric layer. A passivation layer is formed above the first polysilicon layer. A second polysilicon layer is formed above the passivation layer. The second polysilicon layer and the passivation layer are removed. A metal layer is formed above the first polysilicon layer. The first polysilicon layer is reacted with the metal layer to silicide the first polysilicon layer. Any un-reacted metal layer is thereafter removed.Type: ApplicationFiled: June 21, 2010Publication date: April 28, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shun Wu LIN, Matt YEH
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Patent number: 7915105Abstract: The present disclosure provides a method for fabricating a semiconductor device. The method includes forming first, second, third, and fourth gate structures on a semiconductor substrate, each gate structure having a dummy gate, removing the dummy gate from the first, second, third, and fourth gate structures, thereby forming first, second, third, and fourth trenches, respectively, forming a metal layer to partially fill in the first, second, third, and fourth trenches, forming a first photoresist layer over the first, second, and third trenches, etching a portion of the metal layer in the fourth trench, removing the first photoresist layer, forming a second photoresist layer over the second and third trenches, etching the metal layer in the first trench and the remaining portion of the metal layer in the fourth trench, and removing the second photoresist layer.Type: GrantFiled: April 29, 2009Date of Patent: March 29, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Matt Yeh, Shun Wu Lin, Chung-Ming Wang, Chi-Chun Chen
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Publication number: 20100240204Abstract: A method for cleaning a diffusion barrier over a gate dielectric of a metal-gate transistor over a substrate is provided. The method includes cleaning the diffusion barrier with a first solution including at least one surfactant. The amount of the surfactant of the first solution is about a critical micelle concentration (CMC) or more. The diffusion barrier is cleaned with a second solution. The second solution has a physical force to remove particles over the diffusion barrier. The second solution is substantially free from interacting with the diffusion barrier.Type: ApplicationFiled: March 8, 2010Publication date: September 23, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Matt YEH, Shun Wu Lin, Hui Ouyang
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Patent number: 7732344Abstract: A method for fabricating a integrated circuit with improved performance is disclosed. The method comprises providing a substrate; forming a hard mask layer over the substrate; forming protected portions and unprotected portions of the hard mask layer; performing a first etching process, a second etching process, and a third etching process on the unprotected portions of the hard mask layer, wherein the first etching process partially removes the unprotected portions of the hard mask layer, the second etching process treats the unprotected portions of the hard mask layer, and the third etching process removes the remaining unprotected portions of the hard mask layer; and performing a fourth etching process to remove the protected portions of the hard mask layer.Type: GrantFiled: June 5, 2009Date of Patent: June 8, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fang Wen Tsai, Matt Yeh, Ming-Jun Wang, Shun Wu Lin, Chi-Chun Chen, Zin-Chang Wei, Chyi-Shyuan Chern
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Patent number: 7727900Abstract: A cleaning sequence usable in semiconductor manufacturing efficiently cleans semiconductor substrates while preventing chemical oxide formation thereon. The sequence includes the sequence of: 1) treating with an HF solution; 2) treating with pure H2SO4; 3) treating with an H2O2 solution; 4) a DI water rinse; and 5) treatment with an HCl solution. The pure H2SO4 solution may include an H2SO4 concentration of about ninety-eight percent (98%) or greater. After the HCl solution treatment, the cleaned surface may be a silicon surface that is free of a chemical oxide having a thickness of 5 angstroms or greater. The invention finds particular advantage in semiconductor devices that utilize multiple gate oxide thicknesses.Type: GrantFiled: February 21, 2006Date of Patent: June 1, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Matt Yeh, Shun Wu Lin, Chi-Chun Chen, Shih-Chang Chen
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Publication number: 20100124823Abstract: A method is provided for fabricating a semiconductor device. The method includes removing a silicon material from a gate structure located on a substrate through a cycle including: etching the silicon material to remove a portion thereof, where the substrate is spun at a spin rate, applying a cleaning agent to the substrate, and drying the substrate; and repeating the cycle, where a subsequent cycle includes a subsequent spin rate for spinning the substrate during the etching and where the subsequent spin rate does not exceed the spin rate of the previous cycle.Type: ApplicationFiled: November 20, 2008Publication date: May 20, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Matt Yeh, Fan-Yi Hsu, Shun Wu Lin, Shu-Yuan Ku, Hui Ouyang
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Publication number: 20100112811Abstract: The present disclosure provides a method for fabricating a semiconductor device. The method includes forming first, second, third, and fourth gate structures on a semiconductor substrate, each gate structure having a dummy gate, removing the dummy gate from the first, second, third, and fourth gate structures, thereby forming first, second, third, and fourth trenches, respectively, forming a metal layer to partially fill in the first, second, third, and fourth trenches, forming a first photoresist layer over the first, second, and third trenches, etching a portion of the metal layer in the fourth trench, removing the first photoresist layer, forming a second photoresist layer over the second and third trenches, etching the metal layer in the first trench and the remaining portion of the metal layer in the fourth trench, and removing the second photoresist layer.Type: ApplicationFiled: April 29, 2009Publication date: May 6, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Matt Yeh, Shun Wu Lin, Chung-Ming Wang, Chi-Chun Chen
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Publication number: 20100048011Abstract: Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process.Type: ApplicationFiled: February 16, 2009Publication date: February 25, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Matt Yeh, Shun Wu Lin, Chi-Chun Chen, Ryan Chia-Jen Chen, Yi-Hsing Chen, Chien-Hao Chen, Donald Y. Chao, Kuo-Bin Huang
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Publication number: 20080060682Abstract: A method for stripping photoresist and cleaning a semiconductor substrate include a high temperature stripping process in a freshly mixed SPM solution followed by cleaning in a water soluble organic co-solvent such as acetone, IPA, methanol, ethanol, butanol, or DMSO. The substrate may undergo back side heating during the SPM solution stripping process and may optionally use nanospraying techniques to direct the water soluble organic co-solvent to the substrate. The method completely strips plasma hardened photoresist using only wet chemical operations.Type: ApplicationFiled: September 13, 2006Publication date: March 13, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Matt Yeh, Shun-Wu Lin, Chi-Chun Chen, Shih-Chang Chen
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Patent number: 7129184Abstract: A method of preparing a silicon layer or substrate surface for growing an epitaxial layer of SiGe thereon. The process comprises removing native oxide from the surface of the silicon with an HF solution, and then oxidizing the exposed silicon surface to form a chemically formed layer of silicon oxide of the process damaged silicon surface. The chemically formed layer of silicon oxide is then removed by a second HF cleaning process so as to leave a smooth silicon surface suitable for growing a SiGe layer.Type: GrantFiled: December 1, 2004Date of Patent: October 31, 2006Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chien Chang, Shun Wu Lin, Pang-Yen Tsai, Tze-Liang Lee, Shih-Chang Chen