Abstract: According to one embodiment, an image output device includes a buffer into which video information input in stream data is written per block, a determination unit configured to determine whether the buffer is in an overflow state due to slow reproduction, and a buffering control unit configured to switch a buffering pattern of the video information based on a determination result of the determination unit.

Abstract: A moving image player device of the present invention includes an interpolated image generating unit that generates an interpolated frame corresponding to a time between two adjacent input frames using two input frames among the plurality of input frames, and a video playing unit that detects a scene change in the video, outputs the plurality of input frames or the interpolated frames in time series based on the detection result, and plays the video at an arbitrary playing speed. When the scene change is detected, the video playing unit skips a display of the interpolated frames corresponding to time between an input frame at the end of a first scene and an input frame at the head of a second scene, and displays an input frame of the second scene or the interpolated frame after the input frame at the end of the first scene or the interpolated frame.

Abstract: According to one embodiment, an image output device includes a buffer into which video information input in stream data is written per block, a determination unit configured to determine whether the buffer is in an overflow state due to slow reproduction, and a buffering control unit configured to switch a buffering pattern of the video information based on a determination result of the determination unit.

Abstract: According to a moving-image playback device of an embodiment of the invention, a frame rate control circuit uses an input interval Tc of a plurality of input images in an input video, a display interval Td of a plurality of display images in a display video, and a time extension magnification N of the display video with respect to the input video as inputs and that outputs the number “m” of images of the same content and a constant “n” greater by one than the number “a” of interpolation images which are each inserted between the input images. The frame rate control circuit outputs the number “m” of images and the constant “n”, which are determined based on a combination (m, n) of a natural number for satisfying an equation of n×m=N×Tc/Td, to the interpolation image generation circuit.

Abstract: A moving image player device of the present invention includes an interpolated image generating unit that generates an interpolated frame corresponding to a time between two adjacent input frames using two input frames among the plurality of input frames, and a video playing unit that detects a scene change in the video, outputs the plurality of input frames or the interpolated frames in time series based on the detection result, and plays the video at an arbitrary playing speed. When the scene change is detected, the video playing unit skips a display of the interpolated frames corresponding to time between an input frame at the end of a first scene and an input frame at the head of a second scene, and displays an input frame of the second scene or the interpolated frame after the input frame at the end of the first scene or the interpolated frame.

Abstract: According to a moving-image playback device of an embodiment of the invention, a frame rate control circuit uses an input interval Tc of a plurality of input images in an input video, a display interval Td of a plurality of display images in a display video, and a time extension magnification N of the display video with respect to the input video as inputs and that outputs the number “m” of images of the same content and a constant “n” greater by one than the number “a” of interpolation images which are each inserted between the input images. The frame rate control circuit outputs the number “m” of images and the constant “n”, which are determined based on a combination (m, n) of a natural number for satisfying an equation of n×m=N×Tc/Td, to the interpolation image generation circuit.

Abstract: An image processor includes a video input unit that counts the number of input pixel data and a command fetch/issue unit calculates, when a command including information concerning a relative position register in which a delay amount from input of pixel data until execution of a command is stored is fetched, a pixel position of processing target pixel data based on the delay amount and a count result and determines, based on the calculated pixel position, whether signal processing should be performed or specifies an operand used in arithmetic operation.

Abstract: A moving image compression-coding device has a pixel determination module configured to determine whether a color of each pixel in a macro block having a plurality of pixels in an input image is a predetermined color, a pixel counter configured to count a number of the pixels having the predetermined color in the macro block, a macro block determination module configured to determine whether a color of the macro block is considered to be the predetermined color according to the count result, and a compression-coded data generator configured to compression-code the input image with a compression ratio depending on the determination result.

Abstract: According to an embodiment, a compiling device compiling a source program written so as to use a frame memory includes a processing delay amount calculator configured to calculate respective processing delay amounts between a plurality of process tasks in the source program on the basis of processing states of pieces of data processed by the process tasks. The compiling device also includes a line memory amount calculator configured to calculate respective line memory sizes required for each of the process tasks on the basis of an access range of a frame memory from which the process task reads data and an instruction code converter configured to convert the plurality of process tasks to instruction codes executable in a pipeline on the basis of the processing delay amounts and the line memory sizes.

Abstract: An image processing apparatus has: a data memory configured to store image data; an RP register configured to hold a two-dimensional address indicating a position of an RP in a frame of image data; and an RP control section configured to control the two-dimensional address held by the RP register on the basis of the width and height of the frame. Furthermore, the image processing apparatus has an address calculation unit configured to, when reading target pixel data is read from the data memory on the basis of an instruction code provided with a field for specifying a two-dimensional relative position from the RP by a combination of two immediate values, calculate an address at which the reading target pixel data is stored, on the basis of the two-dimensional address, the combination of immediate values and the width of the frame.

Abstract: A memory controller, on receiving a write request to write write-data into an address of a second memory region issued by a processor, determines whether read-data requested to be read from an address of a first memory region by the processor is matched with the write-data requested to be written into the address of the second memory region, and if the read-data is matched with the write-data, prevents the write-data from being written into the address of the second memory region.

Abstract: According to an embodiment, a compiling device compiling a source program written so as to use a frame memory includes a processing delay amount calculator configured to calculate respective processing delay amounts between a plurality of process tasks in the source program on the basis of processing states of pieces of data processed by the process tasks. The compiling device also includes a line memory amount calculator configured to calculate respective line memory sizes required for each of the process tasks on the basis of an access range of a frame memory from which the process task reads data and an instruction code converter configured to convert the plurality of process tasks to instruction codes executable in a pipeline on the basis of the processing delay amounts and the line memory sizes.

Abstract: A moving image compression-coding device has a pixel determination module configured to determine whether a color of each pixel in a macro block having a plurality of pixels in an input image is a predetermined color, a pixel counter configured to count a number of the pixels having the predetermined color in the macro block, a macro block determination module configured to determine whether a color of the macro block is considered to be the predetermined color according to the count result, and a compression-coded data generator configured to compression-code the input image with a compression ratio depending on the determination result.

Abstract: A video coding device includes: a detecting unit configured to detect a foreground region, a background image and a shadow region reflected on the background image by the foreground region in an input picture; a shadow information compressing unit configured to perform a compression process to compress the information quantity of the shadow region; and a coding unit configured to code the foreground region, the background image and the information on the shadow region subjected to the compression process.

Abstract: A compiling apparatus includes an instruction-sequence-hierarchy-graph generating unit that generates an instruction sequence hierarchy graph by arraying unit graphs, to each of which a data path realized by a plurality of microinstructions included in one instruction sequence is to be allocated and in each of which function units included in a target processor are a node and a data line between the function units is an edge, to correspond to an execution order of a plurality of instruction sequences and by connecting arrayed unit graphs with an edge corresponding to a hardware path capable of establishing a data path across the instruction sequences; a data path allocating unit that allocates a data path to each of the unit graphs constituting the instruction sequence hierarchy graph; and an object program output unit that generates an instruction sequence group based on the data path allocated to the instruction sequence hierarchy graph.

Abstract: A microprocessor that can perform sequential processing in data array unit includes: a load store unit that loads, when a fetched instruction is a load instruction for data, a data sequence including designated data from a data memory in memory width unit and specifies, based on an analysis result of the instruction, data scheduled to be designated in a load instruction in future; and a data temporary storage unit that stores use-scheduled data as the data specified by the load store unit.

Abstract: An image processor includes a video input unit that counts the number of input pixel data and a command fetch/issue unit calculates, when a command including information concerning a relative position register in which a delay amount from input of pixel data until execution of a command is stored is fetched, a pixel position of processing target pixel data based on the delay amount and a count result and determines, based on the calculated pixel position, whether signal processing should be performed or specifies an operand used in arithmetic operation.

Abstract: An input unit that sequentially writes a digital image signal to be input in a first buffer while counting number of pixels of the digital image signal, and that writes the written digital image signal in a second buffer; and a command fetching/issuing unit that calculates a position of a pixel based on process delay information that is added to an image processing command and that indicates a delay amount required until image processing by the command is started since the input of the digital image signal, and a counter value indicating the number of pixels, and that issues the image processing command when the position of the pixel is in a valid area are included. Image processing is performed on pixels written in the second buffer based on the issued image processing command.

Abstract: An image processing apparatus has: a data memory configured to store image data; an RP register configured to hold a two-dimensional address indicating a position of an RP in a frame of image data; and an RP control section configured to control the two-dimensional address held by the RP register on the basis of the width and height of the frame. Furthermore, the image processing apparatus has an address calculation unit configured to, when reading target pixel data is read from the data memory on the basis of an instruction code provided with a field for specifying a two-dimensional relative position from the RP by a combination of two immediate values, calculate an address at which the reading target pixel data is stored, on the basis of the two-dimensional address, the combination of immediate values and the width of the frame.

Abstract: A memory controller controls a memory access to each memory region out of one or more memory regions in SIMD unit. The memory controller includes: a pointer-calculation hardware unit that increments by unit SIMD a value of an access control pointer corresponding to each of the memory regions at different timings corresponding to an access mode set beforehand in each memory region; and a memory-access-control hardware unit that calculates an access destination address in each of the memory regions based on a value of an access control pointer in the memory region, and causes a memory access in SIMD unit to be performed to the calculated access destination address.