Abstract: Disclosed herein is a presumably defective portion decision apparatus, including: an arithmetic operation section configured to divide a level difference included in level difference data which indicate a level difference distribution on the surface of a semiconductor device into two or more unit level differences in the depthwise direction of the level difference and determine, for each of the unit level differences obtained by the division, a relationship between the height of a contour line at a level difference position of an upper face and an area of an opening surrounded by the contour line to decide presence or absence of a presumably defective portion.

Abstract: A solid-state imaging device includes a semiconductor layer where a pixel is formed in a pixel region and a semiconductor element is formed in a side opposite to where incident light is incident, a wiring layer provided on the semiconductor layer to cover the semiconductor element, a support substrate provided to oppose the wiring layer in a wiring layer surface opposite to the semiconductor layer, and an adhesion layer which adheres the wiring layer and the support substrate, where the wiring layer includes a pad electrode and an opening is formed so the pad electrode is exposed, a convex section is provided where the pad electrode is formed in at least a wiring layer surface opposing the support substrate or a support substrate surface opposing the wiring layer, and the adhesion layer is formed thinner at the formation portion of the pad electrode than a portion of the pixel region.

Abstract: A method for manufacturing a semiconductor device includes the steps of reading physical layout data of a circuit to be manufactured and performing calculation to modify a pattern width in the physical layout data by a predetermined amount; reading a physical layout and analyzing a pattern that is predicted to remain as a step difference of a predetermined amount or more in a case where a planarization process is performed on a planarizing film on a pattern by a quantitative calculation by using at least one of a density of patterns, a pattern width, and a peripheral length of a range of interest and a range in the vicinity of the range of interest; and reading data of the pattern that is predicted to remain as a step difference, and making a correction to a layout in which a step difference of a predetermined amount or more does not remain.

Abstract: A solid-state imaging device includes a semiconductor layer where a pixel is formed in a pixel region and a semiconductor element is formed in a side opposite to where incident light is incident, a wiring layer provided on the semiconductor layer to cover the semiconductor element, a support substrate provided to oppose the wiring layer in a wiring layer surface opposite to the semiconductor layer, and an adhesion layer which adheres the wiring layer and the support substrate, where the wiring layer includes a pad electrode and an opening is formed so the pad electrode is exposed, a convex section is provided where the pad electrode is formed in at least a wiring layer surface opposing the support substrate or a support substrate surface opposing the wiring layer, and the adhesion layer is formed thinner at the formation portion of the pad electrode than a portion of the pixel region.

Abstract: A method for manufacturing a semiconductor device includes the steps of reading physical layout data of a circuit to be manufactured and performing calculation to modify a pattern width in the physical layout data by a predetermined amount; reading a physical layout and analyzing a pattern that is predicted to remain as a step difference of a predetermined amount or more in a case where a planarization process is performed on a planarizing film on a pattern by a quantitative calculation by using at least one of a density of patterns, a pattern width, and a peripheral length of a range of interest and a range in the vicinity of the range of interest; and reading data of the pattern that is predicted to remain as a step difference, and making a correction to a layout in which a step difference of a predetermined amount or more does not remain.

Abstract: A polishing pad which ensures that a work can be easily removed from the polishing pad surface after polishing, the amount of a polishing liquid used for polishing can be reduced, and the production cost of the polishing pad can be lowered. A first polishing pad (1) for polishing a work is provided with a plurality of slots (11) piercing the first polishing pad (1) in a sa direction, the length in the longitudinal direction of the slots (11) being preferably not less than 20 mm, the pitch in the width direction of the slots (11) being preferably less than 100 mm, and small holes (not shown) may be provided in addition to the slots (11).

Abstract: A manufacturing method of a semiconductor device, comprising providing a low-relative-dielectric-constant film above a substrate containing at least oxygen and having a relative dielectric constant of 3.3 or more, a conductor being to be buried in the film, performing a plasma processing by discharging a gas containing a noble gas as a main component to the film, the plasma processing being executed while the substrate above which the film is provided is storing in a processing chamber having an inside covered with a material composed of an element except for oxygen and substantially set under an oxygen-free atmosphere, and providing a first insulating film above the low-relative-dielectric-constant film by a plasma CVD method, being made of a material containing at least one of a material containing oxygen and a material containing an element reacting with oxygen, a conductor being to be buried in the first insulating film.

Abstract: A polishing pad which ensures that a work can be easily removed from the polishing pad surface after polishing, the amount of a polishing liquid used for polishing can be reduced, and the production cost of the polishing pad can be lowered. A first polishing pad (1) for polishing a work is provided with a plurality of slots (11) piercing the first polishing pad (1) in a sa direction, the length in the longitudinal direction of the slots (11) being preferably not less than 20 mm, the pitch in the width direction of the slots (11) being preferably less than 100 mm, and small holes (not shown) may be provided in addition to the slots (11).

Abstract: In a chemical mechanical polishing apparatus in accordance with the present invention, a material having a hardness defined by JIS standard K6301 (A type) of 10-40 and a thickness of 5-30 mm is used as an elastic member (16) arranged between a polishing pad (12) and a platen (36). Therefore, both flatness and uniformity of a wafer can be sufficiently improved.

Abstract: In a chemical mechanical polishing apparatus in accordance with the present invention, a material having a hardness defined by JIS standard K6301 (A type) of 10-40 and a thickness of 5-30 mm is used as an elastic member (16) arranged between a polishing pad (12) and a platen (36). Therefore, both flatness and uniformity of a wafer can be sufficiently improved.